MP6529 – 5V TO 35V, THREE-PHASE BLDC MOTOR PRE-DRIVER
MP6529 Rev. 1.0 www.MonolithicPower.com 11
10/26/2015 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2015 MPS. All Rights Reserved.
OPERATION
The MP6529 is a three-phase, BLDC motor pre-
driver that can drive three half-bridges with a
0.8A source and a 1A sink current capability over
a wide input voltage range of 5V to 35V. It is
designed for use in battery-powered equipment.
The MP6529 features a low-power sleep mode,
which disables the device and draws a very low
supply current.
The MP6529 provides several flexible functions,
such as adjustable dead-time control and over-
current protection (OCP), which allow the device
to cover a wide range of application fields.
Input Logic
Drive nSLEEP low to put the device into a low-
power sleep state. In this state, all of the internal
circuits are disabled. When nSLEEP is in active
low, all of the inputs are ignored. When exiting
sleep mode, a brief time period of approximately
1ms must pass before issuing a PWM command.
This time period allows the internal circuitry to
stabilize.
ENx controls the gate driver outputs of this phase.
When ENx is low, the gate driver outputs are
disabled, and the PWM inputs are ignored. When
ENx is high, the gate driver outputs are enabled,
and the PWM inputs are recognized. Refer to
Table 1 below for the logic truth table.
Table 1: Input Logic Truth Table
ENx PWMx SHx
H H VIN
H L GND
L x High impendence
nFAULT
nFAULT reports to the system when a fault
condition is detected, such as OCP and OTP.
nFAULT can be an open-drain output, and is
driven low once a fault condition occurs. If the
fault condition is released, nFAULT is pulled high
by an external pull-up resistor.
Over-Current Protection (OCP)
The MP6529 implements VDS sensing circuitry
to protect the power stage from damage caused
by high currents. Based on the R
DS-ON
of the
power MOSFETs and the maximum allowed I
DS
,
a voltage threshold can be calculated, which
triggers the over-current protection (OCP) feature
when exceeded.
This voltage threshold level is programmable
through the OC_REF terminal by applying an
external reference voltage with a DAC. Also,
OCP occurs if the LSS voltage exceeds 0.5V.
Once an OCP event is detected, the MP6529 will
enter a latched fault state and disable all
functions. The MP6529 will stay latched off until it
is reset by nSLEEP or UVLO.
OCP Deglitch Time
Usually, a current spike occurs during the
switching transition due to either the body diode’s
reverse-recovery current or the distributed
inductance or capacitance. This current spike
requires filtering to prevent it from erroneously
triggering OCP and shutting down the external
MOSFET. An internal fixed deglitch time (t
OC
)
(which is also the minimum on time for the
MOSFET) blanks the output of the VDS monitor
when the outputs are switched.
Dead-Time Adjustment
To prevent a shoot-through at any phase of the
bridge, it is necessary to have a dead time (t
DEAD
)
between a high- or low-side turn-off and the next
complementary turn-on event. The dead time for
all three phases is set by a single dead-time
resistor (R
DT
) between DT and ground and is
calculated with Equation (1):
t
DEAD
(nS) = 3.7*R(kΩ) (1)
If DT is tied to GND directly, an internal minimum
dead time of 30ns is applied. Leaving DT open
generates a 6µs dead time.
Input UVLO Protection
If at any time the voltage on VIN falls below the
under-voltage lockout threshold voltage, all
circuitry in the device is disabled, and the internal
logic resets. Operation resumes when VIN rises
above the UVLO threshold.
Thermal Shutdown
If the die temperature exceeds its safe limits, the
MP6529 enters a latched fault-state similar to an
OCP event, and nFAULT is driven low. Only a
reset by nSLEEP or UVLO unlatches the device
from an OTP fault lockout.
