16
FN9101.6
August 6, 2007
to the Processor power pins; they are placed carefully so they
do not to add inductance in the circuit board traces, which could
cancel the usefulness of these low inductance components.
Specialized low-ESR capacitors intended for switching
regulator applications are recommended for the bulk
capacitors. The bulk capacitors ESR and ESL determine the
output ripple voltage and the initial voltage drop following a
high slew-rate transient edge. Recommended are at least (4)
4V, 220µF Sanyo Sp-Cap capacitors in parallel, or (5) 330µF
SP-Cap style capacitors. These capacitors provide an
equivalent ESR of less than 3mΩ. These components
should be laid out very close to the load.
As the sense trace for VSEN may be long and routed close
to switching nodes, a 1.0µF ceramic decoupling capacitor is
located between VSEN and ground at the ISL6218 package.
Output Inductor Selection
The output inductor is selected to meet the voltage ripple
requirements and minimize the converter response time to a
load transient.
The inductor selected for the power channel determines the
channel ripple current. Increasing the value of inductance
reduces the total output ripple current and total output
voltage ripple, but will slow the converter response time to a
load transient.
One of the parameters limiting the converter’s response time to
a load transient is the time required to slew the inductor current
from its initial current level to the transient current level. During
this interval, the difference between the two levels must be
supplied by the output capacitance. Minimizing the response
time can minimize the output capacitance required.
The channel ripple current is approximated by Equation 7:
Input Capacitor Selection
Use a mix of input bypass capacitors to control the voltage
overshoot across the MOSFETs. Use ceramic capacitors for
the high frequency decoupling and bulk capacitors to supply
the RMS current. Small ceramic capacitors must be placed
very close to the upper MOSFET to suppress the voltage
induced in the parasitic circuit impedances.
Two important parameters to consider when selecting the
bulk input capacitor are the voltage rating and the RMS
current rating. For reliable operation, select a bulk capacitor
with voltage and current ratings above the maximum input
voltage and largest RMS current required by the circuit. The
capacitor voltage rating should be at least 1.25 times greater
than the maximum input voltage and a voltage rating of 1.5
times is a conservative guideline.
MOSFET Selection and Considerations
For the Intel IMVP-IV
application that requires up to 20A of
current, it is suggested that Single-Phase channel operation,
with a minimum of (4) MOSFETs per channel, be
implemented. This configuration would be: (2) High
Switching Frequency, Low Gate Charge MOSFET for the
Upper; and (2) Low r
DS(ON)
MOSFETs for the Lowers.
In high-current PWM applications, the MOSFET power
dissipation, package selection and heatsink are the
dominant design factors. The power dissipation includes two
loss components: conduction loss and switching loss. These
losses are distributed between the upper and lower
MOSFETs according to duty cycle of the converter. Refer to
Equations 8 and 9. The conduction losses are the main
component of power dissipation for the lower MOSFETs.
Only the upper MOSFETs have significant switching losses,
since the lower devices turn on and off into near zero
voltage. The following equations assume linear voltage-
current transitions and do not model power loss due to the
reverse-recovery of the lower MOSFET’s body diode. The
gate-charge losses are dissipated in the ISL6218 drivers and
do not heat the MOSFETs; however, large gate-charge
increases the switching time t
SW
, which increases the upper
MOSFET switching losses. Ensure that both MOSFETs are
within their maximum junction temperature at high ambient
temperature by calculating the temperature rise according to
package thermal-resistance specifications.
Typical Application - Single Phase
Converter Using ISL6218 PWM Controller
Figure 12 shows the ISL6218, Synchronous Buck Converter
circuit, which is used to provide the CORE voltage regulation
for the Intel IMVP-IV
application. The circuit uses a single
power channel to deliver up to 20A steady state current, and
has a 330kHz channel switching frequency. For thermal
compensation, a PTC resistor is used as sense resistors.
The Output capacitance is less than 3mΩ of ESR and is (4)
220µF, 4V Sp-Cap parts in parallel with (35) high frequency,
10µF ceramic capacitors.
(EQ. 7)
IN
OUT
SW
OUTIN
CH
V
V
LF
VV
I
=Δ
(EQ. 8)
()
2
FtVI
V
VrI
P
SWSWINO
IN
OUTONDS
2
O
UPPER
×××
+
××
=
(EQ. 9)
()
()
IN
OUTINONDS
2
O
LOWER
V
VVrI
P
××
=
ISL6218
17
FN9101.6
August 6, 2007
FIGURE 12. TYPICAL APPLICATION CIRCUIT FOR THE ISL6218, IMVP-IV
CORE VOLTAGE REGULATOR
ANALOG
POWER
VDD
DACOUT
DSV
FSET
EN
DRSEN
DSEN
VID0
VID1
VID2
VID3
VID4
VID5
PGOOD
EA+
COMP
FB
SOFT
VBAT
ISEN
PHASE
UG
BOOT
VSSP
LG
VDDP
VSEN
DRSV
STV
OCSET
VSS
0.012µF
4 x 220µF
35 x 10µF
2 x SI4362DY
2 x IRF7811W
0.8µH
ETQ-P3H0R8BA
VR_ON
DPSLP
VID
VBATTERY
+5VDC
+5VDC
+VCC_CORE
36.5k_1%
30.1k_1%
49.9k_1%
8 x 10µF
1.5k_1%PTC
3.57k_1%
14k_1%
3300pF
4.64k_1%
1µF
1.2k__1%
174k_1%
4.7µF
1800pF
No-POP
No-POP
560pF
0.33µF
10_1%
1R5_5%
0.027µF
BAT54
NC
NC
NC
NC
NC
NC
NC
ISL6218
TSSOP
98.8k__1%
AND
ISL6218
18
FN9101.6
August 6, 2007
ISL6218
Package Outline Drawing
L40.6x6
40 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 3, 10/06
located within the zone indicated. The pin #1 indentifier may be
Unless otherwise specified, tolerance : Decimal ± 0.05
Tiebar shown (if present) is a non-functional feature.
The configuration of the pin #1 identifier is optional, but must be
between 0.15mm and 0.30mm from the terminal tip.
Dimension b applies to the metallized terminal and is measured
Dimensions in ( ) for Reference Only.
Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
6.
either a mold or mark feature.
3.
5.
4.
2.
Dimensions are in millimeters.1.
NOTES:
(4X)
0.15
INDEX AREA
PIN 1
A
6.00
B
6.00
31
36X
0.50
4.5
4X
40
PIN #1 INDEX AREA
BOTTOM VIEW
40X 0 . 4 ± 0 . 1
20
B0.10
11
MAC
4
21
4 . 10 ± 0 . 15
0 . 90 ± 0 . 1
C
SEATING PLANE
BASE PLANE
0.08
0.10
SEE DETAIL "X"
C
C
0 . 00 MIN.
DETAIL "X"
0 . 05 MAX.
0 . 2 REF
C
5
SIDE VIEW
1
10
30
TYPICAL RECOMMENDED LAND PATTERN
( 5 . 8 TYP )
( 4 . 10 )
( 36X 0 . 5 )
( 40X 0 . 23 )
( 40X 0 . 6 )
6
6
TOP VIEW
0 . 23 +0 . 07 / -0 . 05

ISL6218CRZ

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
IC CTRLR IMPVP-IV SGL-PHS 40-QFN
Lifecycle:
New from this manufacturer.
Delivery:
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