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MAX16009TG+

P1-P3P4-P6P7-P9P10-P12P13-P13
MAX16008/MAX16009
Low-Voltage, High-Accuracy, Quad Window
Voltage Detectors in Thin QFN
10 ______________________________________________________________________________________
Use the following formulas to calculate the error:
where E
UV
and E
OV
are the undervoltage and over-
voltage error (in %), respectively.
2) Calculate R3 based on R
TOTAL
and the desired
upper trip point:
3) Calculate R2 based on R
TOTAL
, R3, and the
desired lower trip point:
4) Calculate R1 based on R
TOTAL
, R3, and R2:
Overvoltage Shutdown
The MAX16008/MAX16009 are ideal for overvoltage-
shutdown applications. Figure 3 shows a typical circuit
for this application using a pass p-channel MOSFET.
The MAX16008/MAX16009 are powered directly from
the system voltage supply. Select R1 and R2 to set the
trip voltage. When the supply voltage remains below the
selected threshold, a low logic level on UVOUT_ turns
on the p-channel MOSFET. In the case of an overvolt-
age event, UVOUT_ goes high turning off the MOSFET,
and shuts down the power to the load.
Figure 4 shows a similar application using a fuse and a
silicon-controlled rectifier (SCR). An overvoltage event
turns on the SCR and shorts the supply to ground. The
surge of current through the short circuit blows the fuse
and terminates the current to the load. Select R3 so that
the gate of the SCR is properly biased when UVOUT_
goes high.
Unused Inputs
Any unused UVIN_ inputs must be connected to V
CC
, and
any unused OVIN_ inputs must be connected to GND.
UVOUT_
/
OVOUT_
Outputs
UVOUT_ and OVOUT_ outputs assert low when UVIN_
and OVIN_, respectively, drop below or exceed their
specified thresholds. The undervoltage/overvoltage out-
puts are open-drain with a (30µA) internal pullup to V
CC
.
For many applications, no external pullup resistor is
required to interface with other logic devices. An external
pullup resistor to any voltage up to 5.5V overdrives the
internal pullup if interfacing to different logic supply volt-
ages. Internal circuitry prevents reverse current flow from
the external pullup voltage to V
CC
(Figure 5). When
choosing the external pullup resistor, the resistance
value should be large enough to ensure that the output
can sink the necessary current during a logic-low condi-
tion and small enough to be able to overdrive the internal
pullup current and meet output high specifications
RR R R
TOTAL
123=−−
R
VxR
V
R
TH TOTAL
TRIPLOW
23=−
E
IR
RR
RR
V
x
E
IR xR
V
x
UV
IB
TRIPLOW
OV
IB
TRIPHIGH
(%)
(%)
(( ))
=
+
+
⎛
⎝
⎜
⎞
⎠
⎟
=
+
1
13
23
21
100
2
100
V
CC
LOAD
UVIN_
R1
R2
UVOUT_
MAX16008/
MAX16009
GND
R3*
V
SUPPLY
*OPTIONAL. VALUES OF 10kΩ AND ABOVE ARE RECOMMENDED.
Figure 3. Overvoltage Shutdown Circuit (with External Pass
MOSFET)
V
CC
LOAD
SCR
UVIN_
R1
R2
R3
UVOUT_
MAX16008/
MAX16009
GND
FUSE
V
SUPPLY
Figure 4. Overvoltage Shutdown Circuit (with SCR Fuse)
MAX16008/MAX16009
Low-Voltage, High-Accuracy, Quad Window
Voltage Detectors in Thin QFN
______________________________________________________________________________________ 11
(V
OH
). Resistor values of 50kΩ to 200kΩ can generally
be used.
RESET
Output (MAX16009 Only)
RESET asserts low when the voltage on any of the
UVIN_ inputs falls below its respective threshold, the
voltage on any of the OVIN_ inputs goes above its
respective threshold, or MR is asserted. RESET
remains asserted for the reset timeout period after all
monitored UVIN_ inputs exceed their respective thresh-
olds, all OVIN_ inputs fall below their respective thresh-
olds, and MR is deasserted (see Figure 6). This
open-drain output has a 30µA internal pullup.
Reset Timeout Capacitor
The reset timeout period can be adjusted to accommo-
date a variety of microprocessor (µP) applications from
50µs to 1.12s. Adjust the reset timeout period (t
RP
) by
connecting a capacitor (C
SRT
) between SRT and GND.
Calculate the reset timeout capacitor as follows:
Do not use capacitor (C
SRT
) values higher than 390nF.
Connect SRT to V
CC
for a factory-programmed reset
timeout of 140ms (min).
Manual Reset Input (
MR
) (MAX16009 Only)
Many µP-based products require manual reset capabil-
ity, allowing the operator, a test technician, or external
logic circuitry to initiate a reset. A logic-low on MR
asserts RESET low. RESET remains asserted while MR
is low, and during the reset timeout period (140ms min)
after MR returns high. The MR input has an internal
20kΩ pullup resistor to V
CC
, so it can be left open if it is
not used. MR can be driven with TTL or CMOS-logic
levels, or with open-drain/collector outputs. Connect a
normally open momentary switch from MR to GND to
create a manual reset function; external debounce cir-
cuitry is not required. If MR is driven from long cables
or if the device is used in a noisy environment, connect-
ing a 0.1µF capacitor from MR to GND provides addi-
tional noise immunity.
Margin Output Disable (
MARGIN
)
MARGIN allows system-level testing while power sup-
plies are adjusted from their nominal voltages. Drive
MARGIN low to deassert all outputs (UVOUT_,
CF
ts
V
I
SRT
RP
TH SRT
SRT
()
()
_
=
⎛
⎝
⎜
⎞
⎠
⎟
MAX16008/
MAX16009
GND
V
CC
GND
RESET
V
CC
5V
UVOUT_
V
CC
= 3.3V
100kΩ
Figure 5. Interfacing to a Different Logic Supply Voltage
UVIN_
10%
90%
10%
90%
RESET
UVOUT_
V
TH_
+ V
TH_HYS
t
RP
t
D
t
D
t
RD
V
TH_
OVIN_
V
TH_
- V
TH_HYS
V
TH_
10%
90%
OVOUT_
t
D
t
D
Figure 6. Output Timing Diagram
Pin Configurations
OVOUT_, and RESET) regardless of the voltage at any
monitored input. The state of each output does not
change while MARGIN = GND. While MARGIN is low,
the IC continues to monitor all voltages. When MARGIN
is deasserted, the outputs go to their monitored states
after a short propagation delay. The MARGIN input is
internally pulled up to V
CC
. Leave unconnected or con-
nect to V
CC
if unused.
Power-Supply Bypassing
The MAX16008/MAX16009 operate from a 2.0V to 5.5V
supply. An undervoltage lockout ensures that the out-
puts are in the correct states when the UVLO is
exceeded. In noisy applications, bypass V
CC
to ground
with a 0.1µF capacitor as close to the device as possi-
ble. In addition, the additional capacitor improves tran-
sient immunity. For fast-rising V
CC
transients, additional
capacitance may be required.
19
20
18
17
7
6
8
OVIN3
OVIN4
GND
9
UVIN3
OVOUT1
OVOUT2
MARGIN
UVOUT1
1
+
+
2
UVIN2
45
15 14 12 11
OVIN2
V
CC
UVOUT4
OVOUT3
UVOUT3
V
CC
MAX16008
UVIN4
UVOUT2
3
13
OVIN1
16
10
OVOUT4
UVIN1
TQFN
4mm x 4mm
TOP VIEW
23
24
22
21
8
7
9
OVIN3
OVIN4
N.C.
GND
10
UVIN3
OVOUT1
OVOUT2
MARGIN
UVOUT1
SRT
12
UVIN2
456
1718 16 14 13
OVIN2
V
CC
UVOUT4
OVOUT3
UVOUT3
V
CC
MAX16009
UVIN4
UVOUT2
3
15
OVIN1
20
11
OVOUT4
UVIN1
19
12
MR
RESET
TQFN
4mm x 4mm
TOP VIEW
MAX16008/MAX16009
Low-Voltage, High-Accuracy, Quad Window
Voltage Detectors in Thin QFN
12 ______________________________________________________________________________________
Selector Guide
PART
NUMBER OF
MONITORED
LEVELS
UNDERVOLTAGE/
OVERVOLTAGE
THRESHOLDS
RESET
ADJUSTABLE
RESET TIMEOUT
MR
MAX16008 4 Adjustable — — —
MAX16009 4 Adjustable ✔✔✔
Package Information
For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a “+”, “#”, or
“-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing per-
tains to the package regardless of RoHS status.
PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO.
20 TQFN-EP T2044+3 21-0139 90-0037
24 TQFN-EP T2444+4 21-0139 90-0022
P1-P3P4-P6P7-P9P10-P12P13-P13

MAX16009TG+

Mfr. #:
Buy MAX16009TG+
Manufacturer:
Maxim Integrated
Description:
Supervisory Circuits Quad Window Monitor
Lifecycle:
New from this manufacturer.
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