LNB Supply and Control Voltage Regulator
A8285 and
A8287
13
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Example.
Given:
V
IN
= 12 V
V
OUT
= 18 V
I
LOAD
= 500 mA
Two-layer PCB.
Maximum ambient temperature = 70 ºC,
Maximum allowed junction temperature= 110 ºC
Assume:
V
D
= 0.4 V and select ΔV
REG
= 0.7 V
D = 1 – (12 / (18 + 0.4 + 0.7) = 0.37
I
PK
= 18
×
0.5 / (0.89
×
12) = 843 mA
R
DSBOOST
= 0.5 + (110
– 25)
×
2.7 mΩ= 730 mΩ
Worst case losses can now be estimated:
Pd_Rds = 0.843
2
×
0.73
×
0.37 = 192 mW
Pd_sw = 70 mW
Pd_control = 15 mA
×
V
IN
= 180 mW
Pd_lin = 0.7
×
0.5 = 350 mW
and therefore
P
TOT
= 0.192 + 0.07 + 0.18 + 0.35 = 0.792 W
The thermal resistance required is:
(110 – 70) / 0.792 = 50.5ºC/W
Note: For the case of the A8287, the area of copper required on
each layer is approximately 1.2 in
2
.
Layout Considerations
Recommended placement of critical components and tracking for
the A8287 is shown in the PCB Layout digagram on the follow-
ing page. It is recommended that the ground plane be separated
into two areas, referred to as switcher and control, on each layer
using a ground plane. With respect to the input connections, VIN
and 0V, the two ground plane areas are isolated as shown by the
dotted line and the ground plane areas are connected together at
pins 6, 7, 18, and 19. This configuration minimizes the effects of
the noise produced by the switcher on the noise-sensitive sections
of the circuit.
Power-related tracking from INPUT to L1, LNB (pin 17) to L2
then OUTPUT, LX (pin 20) to D1 and L1, VBOOST (pin 23)
to C4 and D1 should be as short and wide as possible. Power
components such as the boost diode D1, inductor L1, and input/
output capacitors C1, C9, and C4, should be located as close as
possible to the IC. The DiSEqC inductor L2 should be located as
far away from the boost inductor L1 to prevent potential magnetic
crosstalk.
The filter capacitor (VREG), charge pump capacitor (VCP),
ac coupling tone detect capacitor (TDI), tone pull-down resis-
tor (TOUT), and LNB output capacitor/protection diode (LNB)
should be located directly next to the appropriate pin.
Where a PCB with two or more layers is used, it is recommended
that four thermal vias be deployed as shown in the PCB Layout
diagram. Note that adding additional vias does not enhance the
thermal characteristics.
40
50
60
70
80
90
100
01234
Area (in
2
)
Thermal Resistance (
0
C/W)
One side Copper
Two side Copper
40
50
60
70
80
01234
Area (in
2
)
Thermal Resistance (
0
C/W)
One side Copper
Two side Copper
R
ØJA
vs. Area Charts
A8285, 16-Pin SOIC A8287, 24-Pin SOIC
Thermal Resistance
(ºC /W)
Thermal Resistance
(ºC /W)
Area (in.
2
)
Area (in.
2
)
