A8287SLBTR Datasheet A8285SLB, A8285SLBTR, A8285SLBTR-T | P10-P12

LNB Supply and Control Voltage Regulator

A8285 and

A8287

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

SDA line before the ninth clock cycle, in order to allow this

handshaking to occur.

During a data read, the A8285/A8287 acknowledges the address

in the same way as in the data write sequence, and then retains

control of the SDA line and send the data to the master. On

completion of the eight data bits, the A8285/A8287 releases

the SDA line before the ninth clock cycle, in order to allow the

master to acknowledge the data. If the master holds the SDA line

low during this Acknowledge bit, the A8285/A8287 responds by

sending another data byte to the master. Data bytes continue to be

sent to the master until the master releases the SDA line during

the Acknowledge bit. When this is detected, the A8285/A8287

stops sending data and waits for a stop signal.

Interrupt Request. The A8285/A8287 also provides an inter-

rupt request pin IRQ, which is an open-drain, active-low output.

This output may be connected to a common IRQ line with a

suitable external pull-up and can be used with other I

C devices

to request attention from the master controller. The IRQ output

becomes active when either the A8285/A8287 first recognizes a

fault condition, or at power-on when the main supply V

and the

internal logic supply V

REG

reach the correct operating condi-

tions. It is only reset to inactive when the I

C master addresses

the A8285/A8287 with the Read/Write bit set (causing a read).

Fault conditions are indicated by the TSD, VUV, and OCP bits

in the status register (see description of OCP for conditions of

use). The DIS and PNG bits do not cause an interrupt. When the

master recognizes an interrupt, it addresses all slaves connected

to the interrupt line in sequence, and then reads the status register

to determine which device is requesting attention. The A8285/

A8287 latches all conditions in the status register until the

completion of the data read.

The action at the resampling point is further defined in the

description for each of the status bits. The bits in the status reg-

ister are defined such that the all-zero condition indicates that the

A8285/A8287 is fully active with no fault conditions.

When V

is initially applied, the I

C interface does not respond

to any requests until the internal logic supply V

REG

has reached

its operating level. Once V

REG

has reached this point, the IRQ

output goes active, and the VUV bit is set. After the A8285/

A8287 acknowledges the address, the IRQ flag is reset. Once the

master reads the status registers, the registers are updated with

the VUV reset.

Control Register (Write Register). All main functions of the

A8285/A8287 are controlled through the I

C interface via the

8-bit Control register. This register allows selection of the output

voltage and current limit, enabling and disabling the LNB output,

and switching the 22 kHz tone on and off. The power-up state is 0

for all of the control functions.

Bit 0 (VSEL0), Bit 1 (VSEL1), and Bit 2 (VSEL2). These

provide incremental control over the voltage on the LNB output.

The available voltages provide the necessary levels for all the

common standards plus the ability to add line compensation in

increments of 333 mV. The voltage levels are defined in the Out-

put Voltage Amplitude Selection table.

Bit 3 (VSEL3). Switches between the low-level and high-level

output voltages on the LNB output. A value of 0 selects the low

level voltage and a value of 1 selects the high level. The low-

level center voltage is 12.709 V nominal, and the high level is

18.042 V nominal. These may be increased, in increments of 333

mV, by using the VSEL2, VSEL1, and VSEL0 control register

bits.

Bit 4 (ODT). When set to 1, enables the ODT feature (disables

the A8285/A8287 if the overcurrent disable time is exceeded

during an overcurrent condition on the output). When set to 0, the

ODT feature is disabled.

0 0 0 1 0 A1 A0 1 AK D6 D5 D4 D3 D2 D1 D0 D7 NAK

Status Data Address Start R Stop

1 2 3 4 5 6 7 8 9

SDA

SCL

IRQ

Fault

Event

Reload

Status Register

Reading the Register After an Interrupt

LNB Supply and Control Voltage Regulator

A8285 and

A8287

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Bit 5 (ENB). When set to 1, enables the LNB output. When set to

0, the LNB output is disabled.

Bit 6 (I

LIM

). Selects the I

LIM

level. When set to 0, the lower limit

(typically 500 mA) is selected. When set to 1, the higher limit

(typically 700 mA), is selected.

Bit 7 (ENT). When set to 1, enables modulation of the LNB out-

put with the the internal 22 kHz tone. Since the I

C interface is

compatible with the 400 kHz transfer speed, this bit may be used

to encode DiSEqC™ 2.0 tone bursts for communication with the

LNB or switcher at the far end of the coaxial cable.

Status Register (I

C Read Register). The main fault condi-

tions: overcurrent, undervoltage, and overtemperature, are all

indicated by setting the relevant bit in the Status register. In

all fault cases, once the bit is set it is not reset until the A8285/

A8287 is read by the I

C master. The current status of the LNB

output is also indicated by DIS. DIS and PNG are the only bits

that may be reset without an I

C read sequence. The normal

sequence of the master in a fault condition is to detect the fault by

reading the Status register, then rereading the Status register until

the status bit is reset, indicating the fault condition has been reset.

The fault may be detected by: continuously polling, responding

to an interrupt request (IRQ), or detecting a fault condition exter-

nally and performing a diagnostic poll of all slave devices. Note

that the fully operational condition of the Status register is all 0s.

This simplifies checking of the status byte.

Bit 0 (TSD). A 1 indicates that the A8285/A8287 has detected an

overtemperature condition and has disabled the LNB output. DIS

is set and the A8285/A8287 does not re-enable the output until

so instructed by writing the relevant bit into the Control register.

The status of the overtemperature condition is sampled on the ris-

ing edge of the ninth clock pulse in the data read sequence. If the

condition is no longer present, then the TSD bit is reset, allowing

the master to re-enable the LNB output if required. If the condi-

tion is still present, then the TSD bit remains at 1.

Bit 1 (OCP) Overcurrent. If the A8285/A8287 detects an over-

current condition for greater than the detection time, and if ODT

is enabled, the LNB output is then disabled. Also, the OCP bit is

set to indicate that an overcurrent has occurred, and the DIS bit is

set. The Status register is updated on the rising edge of the ninth

clock pulse. The OCP bit is reset in all cases, allowing the master

to re-enable the LNB output. If the overcurrent timer is not

enabled, the A8285/A8287 operates in current limit indefinitely,

and the OCP bit is not set.

Bit 2 and 3. Reserved.

Bit 4 (PNG) Power Not Good. Set to 1 when the LNB output is

enabled and the LNB output volts are below 85% of the pro-

grammed LNB voltage. The PNG is reset when the LNB volts

are within 90% of the programmed LNB voltage.

Bit 5 (DIS) LNB output disabled. DIS is used to indicate the

current condition of the LNB output. At power-on, or if a fault

condition occurs, the disable bit is set. Having this bit change to

1 does not cause the IRQ to activate because the LNB output may

be disabled intentionally by the I

C master. This bit also is reset

at the end of a write sequence, if the LNB output is enabled.

Bit 6. Reserved.

Bit 7 (VUV) Undervoltage lockout. Set to 1 to indicate that the

A8285/A8287 has detected that the input supply V

is, or has

been, below the minimum level and that an undervoltage lockout

has occurred, which has disabled the LNB output. Bit 5 also is

set, and the A8285/A8287 does not re-enable the output until so

instructed (by having the relevant bit written into the Control reg-

ister). The status of the undervoltage condition is sampled on the

rising edge of the ninth clock pulse in the data read sequence. If

the condition is no longer present, the VUV bit is reset, allowing

the master to re-enable the LNB output if required. If the condi-

tion is still present, the VUV bit remains set to 1.

Bit Name Function

0 VSEL0

See Output Voltage Amplitude

Selection Table

1 VSEL1

2 VSEL2

3 VSEL3

0: LNBx = Low range

1: LNBx = High range

4 ODT

0: Overcurrent disable time off

1: Overcurrent disable time on

5 ENB

0: Disable LNB Output

1: Enable LNB Output

6 ILIM

0: Overcurrent Limit = 500mA

1: Overcurrent Limit = 700mA

7 ENT

0: Disable Tone

1: Enable 22KHz internal tone

Control (Write) Register Table

LNB Supply and Control Voltage Regulator

A8285 and

A8287

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Power Dissipation

To ensure that the device operates within the safe operating

temperature range, several checks should be performed. An

approximate operating junction temperature can be determined by

estimating the power losses and the thermal impedance character-

istics of the printed circuit board solution. To do so, perform the

following procedure:

1. Estimate the maximum ambient temperature (T

2. Define the maximum running junction temperature (T

)of

A8285/A8287. Note that the absolute maximum junction tem-

perature should never exceed 150ºC.

3. Determine worst case power dissipation:

(a) Estimate the duty cycle D:

D = 1 – [V

/ (V

OUT

+ V

+ ΔV

REG

)]

where:

is the voltage drop of the boost diode, and

ΔV

REG

can be taken from the specification table.

(b) Estimate the peak current in boost stage I

= V

OUT

[ I

LOAD

/ (0.89

)]

DSBOOST

) at maximum running junc-

tion temperature. R

DSBOOST

is a function of junction temperature

Bit Name Function

0 TSD Thermal Shutdown

1 OCP Overcurrent

2 Reserved

3 Reserved

4 PNG Power Not Good

5 DIS LNB output disabled

6 Reserved

7 VUV V

Undervoltage

Status (Read) Register Table

and it rises by 2.7 mΩ/ºC with respect to the specified figure,

DSBOOST(25ºC)

, when T

equals 25ºC.

Actual R

DSBOOST

= R

DSBOOST(25ºC)

+ [(T

– 25)

2.7 mΩ]

(d) Determine losses in each block P

TOT

; based on the relative

value of V

, perform either (i) or (ii):

(i) When V

< V

OUT

+ V

+ ΔV

REG

. Note that worst case dis-

sipation occurs at minimum input voltage.

TOT

= Pd_Rds + Pd_sw + Pd_control + Pd_lin

where

Pd_Rds = I

DSBOOST

Pd_control = 15 mA

Pd_lin = ΔV

REG

LOAD

and Pd_sw (switching losses estimate); worst case = 70 mW.

(ii) When V

> V

OUT

+ V

+ ΔV

REG

. Note that worst case dis-

sipation in this case occurs at maximum input voltage.

TOT

= Pd_control + Pd_lin

where:

Pd_control = 15 mA

Pd_lin = (V

– V

OUT

)

LOAD

Step 4. Determine the thermal impedance required in the solu-

tion:

ØJA

= (T

– T

) / P

TOT

The R

ØJA

for one or two layer PCBs can be estimated from the

ØJA

vs. Area charts on the following page.

Note: For maximum effectiveness, the PCB area underneath the

IC should be filled copper and connected to pins 4 and 13 for

A8285, and pins 6, 7, 18, and 19 for A8287. Where a PCB with

two or more layers is used, apply thermal vias, placing them adja-

cent to each of the above pins, and underneath the IC.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18

A8287SLBTR

Mfr. #:

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A8287SLBTR

A8287SLBTR

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