1
IDTAMB0480
ADVANCED MEMORY BUFFER FOR FULLY BUFFERED DIMM
COMMERCIAL TEMPERATURE RANGE
APRIL 2006
2006 Integrated Device Technology, Inc. DSC - 7042/2c
COMMERCIAL TEMPERATURE RANGE
FEATURES:
Advanced Memory Buffer for Fully buffered DIMMs
3.2 and 4 Gbit/s serial speeds (DDR2-533 and 667 DRAM)
Support for up to eight DIMMs per channel
Repeater Mode for extending FB-DIMM links
Northbound and Southbound single lane fail over and channel
error detection
Voltage and Timing margin high-speed I/O test capability
Fully Supports the FB-DIMM configuration register set
Test features supported include:
- Integrated thermal sensor and status indicator
- Supports MEMBIST, IBIST and Virtual Host mode
- Transparent mode and direct access mode for DRAM testing
Complies with JEDEC Architecture and Protocol Specification
Available in 655 ball FCBGA package
EXPANDED FEATURES:
Wide range DDR Timing Control
Superfine adjustment for DDR timing
Wide range of DDR slew rate control
Slew rate controllable independent of output impedance
High speed SMBus in test mode
IBIST IDT PRBS Generator
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
DESCRIPTION:
The fully buffered dual in-line memory module (FB-DIMM) is the next
generation memory architecture to meet the growing memory requirement of
servers and workstations. The IDT Advanced Memory Buffer (AMB) chip is the
essential building block located on each FB-DIMM. The IDT AMB receives
commands and data from the host controller to control and write/read data to/
from the DRAMs on the DIMM. Commands and write data are sent southbound
from the host controller to AMBs in a daisy chain fashion and interpreted by the
target AMB. Status and read data are sent northbound from AMBs to the host
controller also in a daisy chain fashion, passing through non-target AMBs. This
unique channel structure alleviates buffer loading issues common in registered
DIMM technology, enabling designers to use a large number of DIMMs within
a single system.
IDTAMB0480 complies with the latest JEDEC defined FB-DIMM Architecture
and Protocol Specification and supports DDR2-533 and DDR2-667 DRAM.
It also enables serial data transfer at 3.2 and 4.0Gbps. The IDTAMB0480
supports servers, workstations, storage devices and communication applications
that support the next generation FB-DIMM architecture.
IDTAMB0480
PRODUCT
BRIEF
ADVANCED MEMORY BUFFER
FOR FULLY BUFFERED DIMM
MODULES
Host
Memory
Controller
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
14
10
Up to 8 modules
DDR2
DDR2
DDR2
DDR2
IDT
AMB
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
IDT
AMB
IDT
AMB
IDT
AMB
FDB MEMORY CHANNEL
2
COMMERCIAL TEMPERATURE RANGE
IDTAMB0480
ADVANCED MEMORY BUFFER FOR FULLY BUFFERED DIMM
CLK[3:0]
A[15:0]A/BA[2:0]A
Thermal
Sensor
SMBus
Controller
SA[2:0]
SCL
SDA
Failover
Link Init FSM
and Control
Cmnd Decode
& CRC Check
IBIST Rx IBIST Tx
SB Link
CSRs
External MemBIST,
DDR Calibration and
DDR IOBIST
Re-sync
FIFO
De-skew
FIFO
Re-skew
FIFO
SIPO PISO
10 x 12b 10 x 12b
CLK[3:0]
32 x 144b
DDR State
Controller
DDR Link
CSRs
Termination
FSM
FBDRES
A[15:0]B/BA[2:0]B
RASA/CASA/WEA
RASB/CASB/WEB
CS[1:0]A/CKE[1:0]A
CS[1:0]B/CKE[1:0]B
BFUNC
Core Control
and CSRs
Reset
Control
RESET
SB clock
CB[7:0]/DQ[63:0]
DQS[17:0]
Write Data
FIFO
DQS[17:0]
Impedance
Control
FSM
DDRC_B12
DDRC_C12
Sync and Idle
Pattern Gen
CRC Gen
& Read FIFO
Failover
Northbound Lanes
Re-sync
FIFO
De-skew
FIFO
Re-skew
FIFO
SIPOPISO
14 x 12b14 x 12b
PN[13:0]/PN[13:0] SN[13:0]/SN[13:0]
Link Init FSM
and Control
IBIST RxIBIST Tx
NB Link
CSRs
SCK Phase-locked
Loop
Clock
Generator
PLLTSTO
NB clock
REF clock
DDR clocks
SCK
DLL
4
19
18
72
3
10 x 2 10 x 2
Southbound Lanes
PS[9:0]/PS[9:0] SS[9:0]/SS[9:0]
Vref
3
4
ODTA
ODTB
14 x 2 14 x 2
144b
144b168b
DDRC_B18
DDRC_C18
DDRC_C14
FUNCTIONAL BLOCK DIAGRAM
3
IDTAMB0480
ADVANCED MEMORY BUFFER FOR FULLY BUFFERED DIMM
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATIONS
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
1 2 3 4 5 6 7 8 9 101112131415
NC NCNC
NC NCNC
NC NCNC
NC NCNC
NC NCNC
NC NCNC
NC NCNC
NC NCNC
NC NCNC
NC NCNC
NC NCNC
NC NCNC
NC NCNC
NC NCNC
NC NCNC
NC NCNC
NC NCNC
NC NCNC
NC NCNC
NC NCNC
NC NCNC
NC NCNC
VSS
V
DD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSS VSS VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS VSS
VSS
VSS
VSS
VSS
VSS VSS
V
CC
FBD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS VSS VSS VSS
VSSVSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
V
SS
APLL
VCC
APLL
A6A
A4A
PN0
PN1
PN2
PN3
PN4
PN0
PN1
PN2
PN3
PN4
RESET
PN5 PN13
RFU
(1)
PN12 PN6 PN7 PN8 PN9 PN10 PN11
FBD
RES
PLL
TSTO
PN5 PN13
RFU
PN12 PN6 PN7 PN8 PN9 PN10 PN11
(1)
SN0
SN1
SN2
SN0
SN1
SN2
SN3 SN4 SN5 SN13 SN12 SN6 SN7 SN8 SN9 SN10
SN3 SN4 SN5 SN13 SN12 SN6 SN7 SN8 SN9 SN10
A15A A14A A12A
A9A A7A
A5AA11A
A2A A1A A3A
A10ABA0A
CASA BA2A
A0A
CKE
0A
VSS
WEA RASA
CKE
1A
BA1A
DQ28 DQ30
DQS
12
VSS
DQS
12
TEST
LO
TEST
DQ19
DQ21
DQS
11
DQ22
CLK2
CLK0
ODT
0A
CS1A CS0A
DQS2
DQS2
DQ20
DQS
11
CLK2
CLK0
RFU
A8A
A13A
DQS3
DQ18
DQ17
DQ23
DQ26
DQS3
DQ16
DQ29
DQ31 DQ27
DQ25
DQ24
DQ4 DQS9
DQ14
DQ12
DQS
10
DQS
10
DQS9
DQ6
DQ13
DQ11
DQ15 DQ9
DQ7
DQ5
DQS1 DQ10
DQS1
DQ8
DQ3 DQS0
DQ1
DQS0
RFU
(1)
RFU
(1)
RFU
DDRC
_C12
DQ0
DQ2
BFUNC
TEST
LO
TEST
LO
DQS8
CB1
RFU RFU RFU
DDRC
_B12
DDRC
_C14
DQS8
CB2
CB0 CB3
DQS
17
VDDVDD
VDD
VDD
VDD
VDD
VDD
VDDVDD
VDDVDD
VCCVCC
VCCVCC
VCCVCC
VCCVCC
VCCVCC
VCCVCC
VCCVCC
VCC
FBD
VCC
FBD
VCC
FBD
VDD
FCBGA
TOP VIEW, LEFT SIDE
NOTE:
1. These pin positions are reserved for forward clocks to be used in future implementations.

AMB0480A5RJ8

Mfr. #:
Manufacturer:
IDT
Description:
Memory Controllers AMB 1.5
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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