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AS7C31025B-12JCNTR

P1-P3P4-P6P7-P9
AS7C31025B
3/24/04, v. 1.3 Alliance Semiconductor P. 4 of 9
®
Read cycle (over the operating range)
3,9
Key to switching waveforms
Read waveform 1 (address controlled)
3,6,7,9
Read waveform 2 (CE and OE controlled)
3,6,8,9
Parameter Symbol
-10 -12 -15 -20
Unit NotesMin Max Min Max Min Max Min Max
Read cycle time t
RC
10 – 12 – 15 – 20 – ns
Address access time t
AA
–10–12–15–20ns 3
Chip enable (
CE
) access time t
ACE
–10–12–15–20ns 3
Output enable (
OE
) access time t
OE
–5–6–7–8ns
Output hold from address change t
OH
3–3–3–3–ns 5
CE
low to output in low Z t
CLZ
3–3–3–3–ns4, 5
CE
high to output in high Z t
CHZ
–3–3–4–5ns4, 5
OE
low to output in low Z t
OLZ
0–0–0–0–ns4, 5
OE
high to output in high Z t
OHZ
–5–6–7–8ns4, 5
Power up time t
PU
0–0–0–0–ns4, 5
Power down time t
PD
– 10 – 12 – 15 – 20 ns 4, 5
Undefined/don’t careFalling inputRising input
Address
D
OUT
Data valid
t
OH
t
AA
t
RC
current
Supply
OE
D
OUT
t
OE
t
OLZ
t
ACE
t
CHZ
t
CLZ
t
PU
t
PD
I
CC
I
SB
50% 50%
Data valid
t
RC1
CE
t
OHZ
AS7C31025B
3/24/04, v. 1.3 Alliance Semiconductor P. 5 of 9
®
Write cycle (over the operating range)
11
Write waveform 1 (WE controlled)
10,11
Write waveform 2 (CE controlled)
10,11
Parameter Symbol
-10 -12 -15 -20
Unit NotesMin Max Min Max Min Max Min Max
Write cycle time t
WC
10–12–15–20– ns
Chip enable (
CE
) to write end t
CW
8 – 9 –10–12– ns
Address setup to write end t
AW
8 – 9 –10–12– ns
Address setup time t
AS
0–0–0–0– ns
Write pulse width t
WP
7–8–9–12– ns
Write recovery time t
WR
0–0–0–0– ns
Address hold from end of write t
AH
0–0–0–0– ns
Data valid to write end t
DW
5–6–8–10– ns
Data hold time t
DH
0–0–0–0– ns 4, 5
Write enable to output in high Z t
WZ
–5–6–7–8 ns 4, 5
Output active from write end t
OW
1–1–1–1– ns 4, 5
t
AW
t
AH
t
WC
Address
WE
D
OUT
t
DH
t
OW
t
DW
t
WZ
t
WP
t
AS
Data valid
D
IN
t
WR
t
AW
Address
CE
WE
D
OUT
t
CW
t
WP
t
DW
t
DH
t
AH
t
WZ
t
WC
t
AS
Data valid
D
IN
t
WR
AS7C31025B
3/24/04, v. 1.3 Alliance Semiconductor P. 6 of 9
®
AC test conditions
Notes
1 During V
CC
power-up, a pull-up resistor to V
CC
on
CE
is required to meet I
SB
specification.
2 This parameter is sampled, but not 100% tested.
3 For test conditions, see AC Test Conditions, Figures A and B.
4t
CLZ
and t
CHZ
are specified with CL = 5 pF, as in Figure B. Transition is measured ±500 mV from steady-state voltage.
5 This parameter is guaranteed, but not 100% tested.
6
WE
is high for read cycle.
7
CE
and
OE
are low for read cycle.
8 Address is valid prior to or coincident with
CE
transition low.
9 All read cycle timings are referenced from the last valid address to the first transitioning address.
10 N/A
11 All write cycle timings are referenced from the last valid address to the first transitioning address.
12 N/A.
13 C = 30 pF, except all high Z and low Z parameters where C = 5 pF.
255
Ω
– Output load: see Figure B.
– Input pulse level: GND to 3.0 V. See Figure A.
– Input rise and fall times: 2 ns. See Figure A.
– Input and output timing reference levels: 1.5 V.
C
13
320
Ω
D
OUT
GND
+3.3 V
168
Ω
Thevenin equivalent:
D
OUT
+1.728 V
Figure B: 3.3 V Output load
10%
90%
10%
90%
GND
+3.0 V
Figure A: Input pulse
2 ns
P1-P3P4-P6P7-P9

AS7C31025B-12JCNTR

Mfr. #:
Buy AS7C31025B-12JCNTR
Manufacturer:
Alliance Memory
Description:
SRAM 1M, 3.3V, 12ns, FAST 128K x 8 Asynch SRAM
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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