Micrel, Inc. MIC2555
December 2006 27
M9999-121406
GPIO Interrupt Mask False
Set & Clear
set – 1Ch
clr – 1Dh
Enables interrupts on transition from TRUE to FALSE
1 Æset = 1, Interrupt on TÆF.
1 Æclr = 0, no interrupt.
GPIO_0 1 rd/s/c bit 0
GPIO_1 1 rd/s/c bit 1
GPIO_2 1 rd/s/c bit 2
1 rd/s/c bit 3
1 rd/s/c bit 4
1 rd/s/c bit 5
1 rd/s/c bit 6
1 rd/s/c bit 7
GPIO Interrupt Mask True
Set & Clear
set – 1Eh
clr – 1Fh
Enables interrupts on transition from FALSE to
TRUE.
1 Æset = 1, Interrupt on FÆT.
1 Æclr = 0, no interrupt.
GPIO_0 1 rd/s/c bit 0
GPIO_1 1 rd/s/c bit 1
GPIO_2 1 rd/s/c bit 2
1 rd/s/c bit 3
1 rd/s/c bit 4
1 rd/s/c bit 5
1 rd/s/c bit 6
1 rd/s/c bit 7
Note:
Access type “rd/s/c” denotes a field that can be read, set to 1 or cleared to 0. The register can be read from either of
the Addresses indicated. When writing to the “set” Address, any 1’s that are written cause the associated bit to be set.
When writing to the “clr” (Clear) Address, any 1s that are written
cause the associated bit to be cleared.
Example Serial Controller Register Settings
Example
Location Condition BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
Target register Initial state 0 0 1 0 1 0 0 0
‘Set’ register
Data loaded into ‘set’
register
1 0 0 0 1 0 0 0
Target register Resulting state 1 0 1 0 1 0 0 0
‘Clear’ register
Data loaded into
‘Clear’ register
1 0 0 0 1 0 0 0
Target register Resulting state 0 0 1 0 0 0 0 0
