Si5010
16 Rev. 1.3
6. Ordering Guide
7. Top Mark
Part Number Package Temperature Lead Finish
Si5010-BM 20-pin QFN –40 to 85 °C 85/15 Pb/Sn
Si5010-GM 20-pin QFN –40 to 85 °C Matte Sn (Pb-free)
Silicon Labs
Part Number
Die Revision (R) Part Designator (Z)
Si5010-BM B B
Si5010-GM B F
Si5010
Rev. 1.3 17
8. Package Outline: Si5010-BM/GM
Figure 11 illustrates the package details for the Si5010-BM/GM. Table 9 lists the values for the dimensions shown
in the illustration.
Figure 11. 20-pin Quad Flat No-Lead (QFN)
Table 9. Package Dimensions
Symbol Millimeters Symbol Millimeters
Min Nom Max Min Nom Max
A 0.85 0.90 D1, E1 3.75 BSC
A1 0.00 0.01 0.05 D2, E2 1.95 2.10 2.25
A2 0.65 0.70 e 0.50 BSC
A3 0.20 REF. θ ——12°
b 0.18 0.23 0.30 L 0.50 0.60 0.75
D, E 4.00 BSC
Notes:
1. Dimensioning and tolerances conform to ASME Y14.5M. - 1994
2. Package warpage MAX 0.05 mm.
3. “b” applies to plated terminal and is measured between 0.20 and 0.25 mm from terminal TIP.
4. The package weight is approximately 42 mg.
5. The mold compound for this package has a flammability rating of UL94-V0 with an oxygen index of 28
minimum/54 typical.
6. The recommended reflow profile for this package is defined by the JEDEC-020B Small Body specification.
20
Bottom View
11
E2
D2
2
3
Top View Side View
A
A1
A2
A3
θ
2
3
E
E1
PIN1 ID
0.50 DIA.
D
b
20
D1
b
ee
L
Si5010
18 Rev. 1.3
9. 4x4 mm 20L QFN Recommended PCB Layout
Symbol Parameter Dimensions
Min Nom Max
A Pad Row/Column Width/Length 2.23 2.25 2.28
D Thermal Pad Width/Height 2.03 2.08 2.13
e Pad Pitch 0.50 BSC
G Pad Row/Column Separation 2.43 2.46 2.48
R Pad Radius 0.12 REF
X Pad Width 0.23 0.25 0.28
Y Pad Length 0.94 REF
Z Pad Row/Column Extents 4.26 4.28 4.31
Notes:
1. All dimensions listed are in millimeters (mm).
2. The perimeter pads are to be Non-Solder Mask Defined (NSMD). Solder mask openings should be designed to leave 60-75 mm
separation between solder mask and pad metal, all the way around the pad.
3. The center thermal pad is to be Solder Mask Defined (SMD).
4. Thermal/Ground vias placed in the center pad should be no less than 0.2 mm (8 mil) diameter and tented from the top to prevent
solder from flowing into the via hole.
5. The stencil aperture should match the pad size (1:1 ratio) for the perimeter pads. A 3x3 array of 0.5 mm square stencil openings, on a
0.65 mm pitch, should be used for the center thermal pad.
6. A stencil thickness of 5 mil is recommended. The stencil should be laser cut and electropolished, with trapezoidal walls to facilitate
paste release.
7. A “No-Clean”, Type 3 solder paste should be used for assembly. Nitrogen purge during reflow is recommended.
8. Do not place any signal or power plane vias in these “keep out” regions.
9. Suggest four 0.38 mm (15 mil) vias to the ground plane.
See Note 8
Gnd Pin
Gnd Pin
Gnd Pin
See Note 9

SI5010-BM

Mfr. #:
Manufacturer:
Silicon Labs
Description:
Clock Generators & Support Products OC-3/12, STM-1/4 Sonet/SDH CDR
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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