1/9June 2001
■ HIGH SPEED: t
PD
= 3.6ns (TYP.) at V
CC
= 5V
■ LOW POWER DISSIPATION:
I
CC
= 4 µA (MAX.) at T
A
=25°C
■ HIGH NOISE IMMUNITY:
V
NIH
= V
NIL
= 28% V
CC
(MIN.)
■ POWER DOWN PROTECTION ON INPUTS
■ SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 8 mA (MIN)
■ BALANCED PROPAGATION DELAYS:
t
PLH
≅ t
PHL
■ OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 5.5V
■ PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 240
■ IMPROVED LATCH-UP IMMUNITY
■ LOW NOISE: V
OLP
= 0.9V (MAX.)
DESCRIPTION
The 74VHC240 is an advanced high-speed
CMOS OCTAL BUS BUFFER (3-STATE)
fabricated with sub-micron silicon gate and
double-layer metal wiring C
2
MOS technology.
G
output enable governs four BUS BUFFERs.
This device is designed to be used with 3 state
memory address drivers, etc.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74VHC240
OCTAL BUS BUFFER
WITH 3 STATE OUTPUTS (INVERTED)
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES
PACKAGE TUBE T & R
SOP 74VHC240M 74VHC240MTR
TSSOP 74VHC240TTR
TSSOPSOP