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MPC941AE

P1-P3P4-P6P7-P9P10-P12
MPC941
MOTOROLA TIMING SOLUTIONS
DL207 — Rev 0
4
Table 5: DC CHARACTERISTICS (V
CC
= 2.5V ± 5%, T
A
= –40 to +85°C)
Symbol Characteristics Min Typ Max Unit Condition
V
IH
Input high voltage LVCMOS_CLK 1.7 V
CC
+ 0.3 V LVCMOS
V
IL
Input low voltage LVCMOS_CLK -0.3 0.7 V LVCMOS
I
IN
Input current ±120
a
µA
V
PP
Peak-to-peak input voltage PECL_CLK,
PECL_CLK
500 mV LVPECL
V
CMR
Common Mode Range PECL_CLK,
PECL_CLK
1.1 V
CC
-0.7 V LVPECL
V
OH
Output High Voltage 1.8 V I
OH
=-15 mA
b
V
OL
Output Low Voltage 0.6 V I
OL
= 15 mA
b
I
OZ
Output tristate leakage current 100 µA
Z
OUT
Output impedance 18 – 20
C
PD
Power Dissipation Capacitance 7–8 10 pF Per Output
C
IN
Input capacitance 4.0 pF
I
CCQ
Maximum Quiescent Supply Current 5 mA All V
CC
Pins
V
TT
Output termination voltage V
CC
÷2 V
a. Input pull-up / pull-down resistors influence input current.
b. The MPC941 is capable of driving 50Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated transmission
line to a termination voltage of V
TT
. Alternatively, the device drives up to two 50Ω series terminated transmission lines.
Table 6: AC CHARACTERISTICS (V
CC
= 2.5V ± 5%, T
A
= –40 to +85°C)
a
Symbol Characteristics Min Typ Max Unit Condition
f
MAX
Maximum Output Frequency 0 250
b
MHz
t
r
, t
f
LVCMOS_CLK Input Rise/Fall Time 1.0
c
ns 0.7 to 1.7V
t
PLH
t
PHL
Propagation delay PECL_CLK to any Q
LVCMOS_CLK to any Q
1.3
1.0
2.1
1.8
2.9
2.6
ns
ns
t
PLZ,
HZ
Output Disable Time ns
t
PZL,
LZ
Output Enable Time ns
t
sk(O)
Output-to-output Skew PECL_CLK to any Q
LVCMOS_CLK to any Q
125
125
250
250
ps
t
sk(PP)
Device-to-device Skew PECL_CLK to any Q
LVCMOS_CLK to any Q
1200
1200
ps
ps
For a given T
A
and V
CC
, any Q
t
sk(PP)
Device-to-device Skew PECL_CLK to any Q
LVCMOS_CLK to any Q
1600
1600
ps
ps
For any T
A
, V
CC
and Q
DC
Q
Output Duty Cycle PECL_CLK to any Q
LVCMOS_CLK to any Q
45
45
50
50
60
55
%
%
DC
REF
= 50%
DC
REF
= 50%
t
r
, t
f
Output Rise/Fall Time 0.2 1.0 ns 0.6 to 1.6V
a. AC characteristics apply for parallel output termination of 50Ω to V
TT
.
b. AC characteristics are guaranteed up to f
max
. Please refer to the applications section for information on power consumption versus operating
frequency and thermal management.
c. Fast input signal transition times are required to maintain part-to-part skew specification. If part-to-part skew is not critical to the application, signal
transition times smaller than 3 ns can be applied to the MPC941.
Frees
cale Semiconductor,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
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MPC941
TIMING SOLUTIONS
DL207 — Rev 0
5 MOTOROLA
APPLICATIONS INFORMATION
Driving Transmission Lines
The MPC941 clock driver was designed to drive high
speed signals in a terminated transmission line environment.
To provide the optimum flexibility to the user the output
drivers were designed to exhibit the lowest impedance
possible. With an output impedance of less than 20Ω the
drivers can drive either parallel or series terminated
transmission lines. For more information on transmission
lines the reader is referred to application note AN1091 in the
Timing Solutions data book (DL207/D).
In most high performance clock networks point–to–point
distribution of signals is the method of choice. In a
point–to–point scheme either series terminated or parallel
terminated transmission lines can be used. The parallel
technique terminates the signal at the end of the line with a
50Ω resistance to VCC/2. This technique draws a fairly high
level of DC current and thus only a single terminated line can
be driven by each output of the MPC941 clock driver. For the
series terminated case however there is no DC current draw,
thus the outputs can drive multiple series terminated lines.
Figure 1 “Single versus Dual Transmission Lines” illustrates
an output driving a single series terminated line vs two series
terminated lines in parallel. When taken to its extreme the
fanout of the MPC941 clock driver is effectively doubled due
to its capability to drive multiple lines.
Figure 1. Single versus Dual Transmission Lines
14Ω
IN
MPC941
OUTPUT
BUFFER
R
S
= 36Ω
Z
O
= 50Ω
OutA
14Ω
IN
MPC941
OUTPUT
BUFFER
R
S
= 36Ω
Z
O
= 50Ω
OutB0
R
S
= 36Ω
Z
O
= 50Ω
OutB1
The waveform plots of Figure 2 “Single versus Dual
Waveforms” show the simulation results of an output driving
a single line vs two lines. In both cases the drive capability of
the MPC941 output buffer is more than sufficient to drive 50Ω
transmission lines on the incident edge. Note from the delay
measurements in the simulations a delta of only 43ps exists
between the two differently loaded outputs. This suggests
that the dual line driving need not be used exclusively to
maintain the tight output–to–output skew of the MPC941.
The output waveform in Figure 2 shows a step in the
waveform, this step is caused by the impedance mismatch
seen looking into the driver. The parallel combination of the
36Ω series resistor plus the output impedance does not
match the parallel combination of the line impedances. The
voltage wave launched down the two lines will equal:
VL = VS ( Zo / (Rs + Ro +Zo))
Zo = 50Ω || 50Ω
Rs = 36Ω || 36Ω
Ro = 14Ω
VL = 3.0 (25 / (18 + 14 + 25) = 3.0 (25 / 57)
= 1.31V
At the load end the voltage will double, due to the near
unity reflection coefficient, to 2.5V. It will then increment
towards the quiescent 3.0V in steps separated by one round
trip delay (in this case 4.0ns).
Figure 2. Single versus Dual Waveforms
TIME (nS)
VOLTAGE (V)
3.0
2.5
2.0
1.5
1.0
0.5
0
2 4 6 8 10 12 14
OutB
t
D
= 3.9386
OutA
t
D
= 3.8956
In
Since this step is well above the threshold region it will not
cause any false clock triggering, however designers may be
uncomfortable with unwanted reflections on the line. To
better match the impedances when driving multiple lines the
situation in Figure 3 “Optimized Dual Line Termination”
should be used. In this case the series terminating resistors
are reduced such that when the parallel combination is added
to the output buffer impedance the line impedance is
perfectly matched.
Figure 3. Optimized Dual Line Termination
14Ω
MPC941
OUTPUT
BUFFER
R
S
= 22Ω
Z
O
= 50Ω
R
S
= 22Ω
Z
O
= 50Ω
14Ω + 22Ω 22Ω = 50Ω 50Ω
25Ω = 25Ω
Frees
cale Semiconductor,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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MPC941
MOTOROLA TIMING SOLUTIONS
DL207 — Rev 0
6
Power Consumption of the MPC941 and Thermal
Management
The MPC941 AC specification is guaranteed for the entire
operating frequency range up to 250 MHz. The MPC941
power consumption and the associated long-term reliability
may decrease the maximum frequency limit, depending on
operating conditions such as clock frequency, supply voltage,
output loading, ambient temperture, vertical convection and
thermal conductivity of package and board. This section
describes the impact of these parameters on the junction
temperature and gives a guideline to estimate the MPC941
die junction temperature and the associated device reliability.
For a complete analysis of power consumption as a function
of operating conditions and associated long term device
reliability please refer to the application note AN1545.
According the AN1545, the long-term device reliability is a
function of the die junction temperature:
Table 7: Die junction temperature and MTBF
Junction temperature (°C) MTBF (Years)
100 20.4
110 9.1
120 4.2
130 2.0
Increased power consumption will increase the die
junction temperature and impact the device reliability
(MTBF). According to the system-defined tolerable MTBF,
the die junction temperature of the MPC941 needs to be
controlled and the thermal impedance of the board/package
should be optimized. The power dissipated in the MPC941 is
represented in equation 1.
Where I
CCQ
is the static current consumption of the
MPC941, C
PD
is the power dissipation capacitance per
output,
(Μ)ΣC
L
represents the external capacitive output
load, N is the number of active outputs (N is always 27 in
case of the MPC941). The MPC941 supports driving
transmission lines to maintain high signal integrity and tight
timing parameters. Any transmission line will hide the lumped
capacitive load at the end of the board trace, therefore,
ΣC
L
is
zero for controlled transmission line systems and can be
eliminated from equation 1. Using parallel termination output
termination results in equation 2 for power dissipation.
In equation 2, P stands for the number of outputs with a
parallel or thevenin termination, V
OL
, I
OL
, V
OH
and I
OH
are a
function of the output termination technique and DC
Q
is the
clock signal duty cyle. If transmission lines are used
ΣC
L
is
zero in equation 2 and can be eliminated. In general, the use
of controlled transmission line techniques eliminates the
impact of the lumped capacitive loads at the end lines and
greatly reduces the power dissipation of the device. Equation
3 describes the die junction temperature T
J
as a function of
the power consumption.
Where R
thja
is the thermal impedance of the package
(junction to ambient) and T
A
is the ambient temperature.
According to Table 7, the junction temperature can be used to
estimate the long-term device reliability. Further, combining
equation 1 and equation 2 results in a maximum operating
frequency for the MPC941 in a series terminated
transmission line system.
T
J,MAX
should be selected according to the MTBF system
requirements and Table 7. R
thja
can be derived from Table 8.
The R
thja
represent data based on 1S2P boards, using 2S2P
boards will result in a lower thermal impedance than
indicated below.
Table 8: Thermal package impedance of the 48ld LQFP
Convection, LFPM R
thja
(1P2S board), K/W
Still air 78
100 lfpm 68
200 lfpm 59
300 lfpm 56
400 lfpm 54
500 lfpm 53
If the calculated maximum frequency is below 250 MHz, it
becomes the upper clock speed limit for the given application
conditions. The following eight derating charts describe the
safe frequency operation range for the MPC941. The charts
were calculated for a maximum tolerable die junction
temperature of 110°C (120°C), corresponding to a estimated
MTBF of 9.1 years (4 years), a supply voltage of either 3.3V
or 2.5V and series terminated transmission line or capacitive
loading. Depending on a given set of these operating
conditions and the available device convection a decision on
the maximum operating frequency can be made.
P
TOT
I
CCQ
V
CC
f
CLOCK
N C
PD
M
C
L
V
CC
Equation 1
P
TOT
V
CC
I
CCQ
V
CC
f
CLOCK
N C
PD
M
C
L
P
DC
Q
I
OH
V
CC
V
OH
1 DC
Q
I
OL
V
OL
Equation 2
T
J
T
A
P
TOT
R
thja
Equation 3
f
CLOCK,MAX
1
C
PD
N V
2
CC
T
J,MAX
T
A
R
thja
I
CCQ
V
CC
Equation 4
Frees
cale Semiconductor,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...
P1-P3P4-P6P7-P9P10-P12

MPC941AE

Mfr. #:
Buy MPC941AE
Manufacturer:
IDT
Description:
Clock Drivers & Distribution FSL 1-27 LVCMOS Fanout Buffer
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