74VHC123AFT,74VHC221AFT
7
12.
12.
12.
12. Functional Description
Functional Description
Functional Description
Functional Description
(1) Standby state
The external capacitor (C
X
) is fully charged to V
CC
in the stand-by state. That means, before triggering,
the Q
P
and Q
N
transistors which are connected to the R
X
/C
X
node are in the off state. Two comparators
that relate to the timing of the output pulse, and two reference voltage supplies turn off. The total supply
current is only leakage current.
(2) Trigger operation
Trigger operation is effective in any of the following three cases. First, the condition where the A input is
low, and the B input has a rising signal; second, where the B input is high, and the A input has a falling
signal; and third, where the A input is low and the B input is high, and the CLR input has a rising signal.
After a trigger becomes effective, comparators C
1
and C
2
start operating, and Q
N
is turned on. The
external capacitor discharges through Q
N
. The voltage level at the R
X
/C
X
node drops. If the R
X
/C
X
voltage
level falls to the internal reference voltage V
ref
L, the output of C
1
becomes low. The flip-flop is then reset
and Q
N
turns off. At that moment C
1
stops but C
2
continues operating.
After Q
N
turns off, the voltage at the R
X
/C
X
node starts rising at a rate determined by the time constant
of external capacitor C
X
and resistor R
X
.
Upon triggering, output Q becomes high, following some delay time of the internal F/F and gates. It stays
high even if the voltage of R
X
/C
X
changes from falling to rising. When R
X
/C
X
reaches the internal
reference voltage V
ref
H, the output of C
2
becomes low, the output Q goes low and C
2
stops its operation.
That means, after triggering, when the voltage level of the R
X
/C
X
node reaches V
ref
H, the IC returns to
its MONOSTABLE state.
With large values of C
X
and R
X
, and ignoring the discharge time of the capacitor and internal delays of
the IC, the width of the output pulse, t
wOUT
, is as follows:
t
wOUT
= 1.0 × C
X
× R
X
(3) Retrigger operation
When a new trigger is applied to either input A or B while in the MONOSTABLE state, it is effective only
if the IC is charging C
X
. The voltage level of the R
X
/C
X
node then falls to V
ref
L level again. Therefore the
Q output stays high if the next trigger comes in before the time period set by C
X
and R
X
.
If the new trigger is very close to previous trigger, such as an occurrence during the discharge cycle, it
will have no effect.
The minimum time for a trigger to be effective 2 nd trigger, t
rr
(min), depends on V
CC
and
C
X
.(74VHC123AFT)
(4) Reset operation
In normal operation, the CLR input is held high. If CLR is low, a trigger has no effect because the Q
output is held low and the trigger control F/F is reset. Also, Q
P
turns on and C
X
is charged rapidly to V
CC
.
This means if CLR is set low, the IC goes into a wait state.
2017-03-08
Rev.7.0
©2016 Toshiba Corporation
