PAM8407
Document number: DS36815 Rev. 1 - 2
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PAM8407
New Product
A PRODUCT LINE OF
DIODES INCORPORATED
2x3W Stereo Differential Input Class D Audio Amplifier
with U
p
/Down Volume Control
Application Information
Maximum Gain
As shown in block diagram, the PAM8407 has two internal amplifiers stage. The first stage's gain is externally con-figurable, while the second
stage's is internally fixed in a fixed-gain, inverting configuration. The closed-loop gain of the first stage is set by selecting the ratio of Rf to Ri while
the second stage's gain is fixed at 2x. Consequently, the differential gain for the IC is
A
VD
= 20*log [2*(Rf/Ri)]
The PAM8407 sets maximum Rf=218k and minimum Ri=27k, thus the maximum closed-gain is 24dB.
UP/DOWN Volume Control (DVC)
The PAM8407 features a UP/DOWN volume control which consists of the UP and DOWN pins. An internal clock is used where the clock
frequency value is determined from the following formula:
f
CLK
= f
OSC
/ 2
13
The oscillator frequency f
OSC
value is 250kHz typical,with ±20% tolerance. The DVC’s clock frequency is 30Hz (cycle time 33ms) typical.
Volume changes are then effected by toggling either the UP or DOWN pins with a logic low. After a period of 1 cycle pulses with either the UP or
DOWN pins held low, the volume will change to the next specified step, either UP or DOWN, and followed by a short delay. This delay decreases
the longer the line is held low, eventually reaching a delay of zero. The delay allows the user to pull the UP or DOWN terminal low once for one
volume change, or hold down to ramp several volume changes. The delay is optimally configured for push button volume control.
If either the UP or DOWN pin remains low after the first volume transition the volume will change again, but this time after 10 cycles. The followed
transition occurs at 4 cycles for each volume transition. This is intended to provide the user with a volume control that pauses briefly after initial
application, and then slowly increases the rate of volume change as it is continuously applied. This cycle is shown in the timing diagram shown in
figure 1.
There are 32 discrete gain settings ranging from +24dB maximum to -80dB minimum. Upon device power on or applied a logic low to the SD pin,
the amplifier's gain is set to a default value of 12dB. Volume levels for each step vary and are specified in Gain Setting table on page 7.
If both the UP and DOWN pins are held high, no volume change will occur. Trigger points for the UP and DOWN pins are at 70% of VDD minimum
for a logic high, and 20% of VDD maximum for a logic low. It is recommended, however, to toggle UP and DOWN between VDD and GND for best
performance.
1 cycle
10 cycles 4 cycles
UP/DN
VOL U ME
LEVEL
4 cycles
Figure 1.Timming Diagram
Shutdown operation
In order to reduce power consumption while not in use, the PAM8407 contains shutdown circuitry that is used to turn off the amplifier's bias
circuitry. This shutdown feature turns the amplifier off when logic low is placed on the SD pin. By switching the SD pin connected to GND, the
PAM8407 supply current draw will be minimized in idle mode. The SD pin cannot be left floating due to the pull-down internal.
PAM8407
Document number: DS36815 Rev. 1 - 2
8 of 12
www.diodes.com
January 2014
© Diodes Incorporated
PAM8407
New Product
A PRODUCT LINE OF
DIODES INCORPORATED
2x3W Stereo Differential Input Class D Audio Amplifier
with U
p
/Down Volume Control
Application Information
(Continued)
Power supply decoupling
The PAM8407 is a high performance CMOS audio amplifier that requires adequate power supply decoupling to ensure the output THD and PSRR
are as low as possible. Power supply decoupling is affecting low frequency response. Optimum decoupling is achieved by using two capacitors of
different types that target different types of noise on the power supply leads. For higher frequency transients, spikes, or digital hash on the line, a
good low equivalent-series-resistance (ESR) ceramic capacitor, typically 1.0µF, placed as close as possible to the device VDD terminal works best.
For filtering lower-frequency noise signals, a larger capacitor of 10µF (ceramic) or greater placed near the audio power amplifier is recommended.
Input Capacitor (Ci)
Large input capacitors are both expensive and space hungry for portable designs. Clearly, a certain sized capacitor is needed to couple in low
frequencies without severe attenu-ation. But in many cases the speakers used in portable systems, whether internal or external, have little ability
to reproduce signals below 100Hz to 150Hz. Thus, using a large input capacitor may not increase actual system perfor-mance. In this case, input
capacitor (Ci) and input resistance (Ri) of the amplifier form a high-pass filter with the corner frequency determined equation below,
In addition to system cost and size, click and pop perfor-mance is affected by the size of the input coupling capacitor, Ci. A larger input coupling
capacitor requires more charge to reach its quiescent DC voltage (nominally 1/2 VDD). This charge comes from the internal circuit via the
feedback and is apt to create pops upon device enable. Thus, by minimizing the capacitor size based on necessary low frequency response, turn-
on pops can be minimized.
Under Voltage Lock-out (UVLO)
The PAM8407 incorporates circuitry designed to detect when the supply voltage is low. When the supply voltage drops to 2.4V or below, the
PAM8407 outputs are disable, and the device comes out of this state and starts to normal functional when the supply voltage increases.
Short Circuit Protection (SCP)
The PAM8407 has short circuit protection circuitry on the outputs that prevents damage to the device during output-to-output and output-to-GND
short. When a short circuit is detected on the outputs, the outputs are disable immediately. If the short was removed, the device activates again.
Over Temperature Protection
Thermal protection on the PAM8407 prevents damage to the device when the internal die temperature exceeds 150°C. There is a 15 degree
tolerance on this trip point from device to device. Once the die temperature exceeds the thermal set point, the device outputs are disabled. This is
not a latched fault. The thermal fault is cleared once the temperature of the die is reduced by 60°C. This large hysteresis will prevent motor
boating sound well and the device begins normal operation at this point with no external system interaction.
How to Reduce EMI (Electro Magnetic Interference)
A simple solution is to put an additional capacitor 1000uF at power supply terminal for power line coupling if the traces from amplifier to speakers
are short (<20cm). Most applications require a ferrite bead filter which shows at Figure 3. The ferrite filter reduces EMI around 1 MHz and higher.
When selecting a ferrite bead, choose one with high impedance at high frequencies, but low impedance at low frequencies.
C
ii
1
f=
2πRC
PAM8407
Document number: DS36815 Rev. 1 - 2
9 of 12
www.diodes.com
January 2014
© Diodes Incorporated
PAM8407
New Product
A PRODUCT LINE OF
DIODES INCORPORATED
2x3W Stereo Differential Input Class D Audio Amplifier
with U
p
/Down Volume Control
Application Information
(Continued)
220pF
220pF
OUT+
OUT-
Ferrite Bead
Ferrite Bead
Figure 3: Ferrite Bead Filter to reduce EMI
PCB Layout Guidelines
Grounding
At this stage it is paramount that we acknowledge the need for separate grounds. Noise currents in the output power stage need to be returned to
output noise ground and nowhere else. Were these currents to circulate elsewhere, they may get into the power supply, the signal ground, etc,
worse yet, they may form a loop and radiate noise. Any of these instances results in degraded amplifier performance. The logical returns for the
output noise currents associated with Class D switching are the respective PGND pins for each channel. The switch state diagram illustrates that
PGND is instrumental in nearly every switch state. This is the perfect point to which the output noise ground trace should return. Also note that
output noise ground is channel specific. A two channels amplifier has two mutually exclusive channels and consequently must have two mutually
exclusive output noise ground traces. The layout of the PAM8407 offers separate PGND connections for each channel and in some cases each
side of the bridge. Output noise grounds must tie to system ground at the power in exclusively. Signal currents for the inputs, reference, etc need
to be returned to quite ground. This ground only ties to the signal components and the GND pin. GND then ties to system ground.
Power Supply Line
As same to the ground, VDD and each channel PVDD need to be separated and tied together at the system power supply. Recommend that all
the trace could be routed as short and thick as possible. For the power line layout, just imagine water stream, any barricade placed in the trace
(shows in figure 4) could result in the bad performance of the amplifier.
Figure 4
Components Placement
The power supply decoupling capacitors need to be placed as close to VDD pins as possible. The inputs need to be routed away from the noisy
trace.

PAM8407DR

Mfr. #:
Manufacturer:
Diodes Incorporated
Description:
Audio Amplifiers 2x3W Stereo Diff D SNR 32-Step 8mA
Lifecycle:
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