LTC6603
16
6603fa
APPLICATIONS INFORMATION
The following graphs show a few of the possible lowpass
lters.
Gain and Group Delay vs Frequency
(2.5MHz Lowpass Response)
Gain and Group Delay vs Frequency
(650kHz Lowpass Response)
The oscillator is sensitive to transients on the positive
supply. The IC should be soldered to the PC board and
the PCB layout should include a 0.1µF ceramic capacitor
between V+
A
(Pin 2) and ground, as close as possible to
the IC to minimize inductance. The PCB layout should also
include an additional 0.1µF ceramic capacitor between
V+
D
(Pin 16) and ground. Avoid parasitic capacitance on
R
BIAS
(Pin 4) and avoid routing noisy signals near R
BIAS
.
Use a ground plane connected to Pin 14 and the Exposed
Pad (Pin 25).
FREQUENCY (Hz)
GAIN (dB)
GROUP DELAY (µs)
6603 G17
0
–20
–100
–80
–60
–40
–120
1.2
1.0
0.2
0.4
0.6
0.8
0
100k 10M1M
GAIN
GROUP DELAY
FREQUENCY (Hz)
GAIN (dB)
GROUP DELAY (µs)
6603 G18
0
–60
–40
–20
–80
1
2
3
4
0
100k 1M
GAIN
GROUP DELAY
Alternative Methods of Setting the Clock Frequency of
the LTC6603
The oscillator may be programmed by any method that
sinks a current out of the R
BIAS
pin. The circuit in Figure 6
sets the clock frequency by using a programmable current
source and in the expression for f
CLK
, the resistor R
BIAS
is replaced by the ratio of 1.17V/I
CONTROL
. Because the
voltage of the R
BIAS
pin is approximately 1.17V ±5%, the
Figure 6 circuit is less accurate than if a resistor controls
the clock frequency.
In this circuit, the LTC2621 (a 12-bit DAC) is daisy-chained
with the LTC6603. Because the sinking current from the
R
BIAS
pin is:
V
RBIAS
•k
2
N
•R1
the equivalent R
BIAS
is:
2
N
•R1
k
,
where k is the binary DAC input code and N is the resolu-
tion. Figure 7 shows some of the frequency responses
that can be obtained using this circuit.
Figure 8 shows the LTC6603’s oscillator confi gured as
a VCO. A voltage source is connected in series with the
R
BIAS
resistor. The clock frequency, f
CLK
, will vary with
V
CONTROL
. Again, this circuit decouples the relationship
between the current out of the R
BIAS
pin and the voltage
of the R
BIAS
pin; the frequency accuracy will be degraded.
The clock frequency, however, will increase monotonically
with decreasing V
CONTROL
.
Operation Using an External Clock
The LTC6603 may be clocked by an external oscillator
for tighter bandwidth control by pulling CLKCNTL (Pin 5)
to ground and driving a clock into CLKIO (Pin 15). If an
external clock is used, the R
BIAS
resistor is still necessary.
The value of R
BIAS
must be no larger than the value that
would be required for using the internal oscillator. For
example, a 100k resistor would program the internal oscil-
lator for 24.705MHz, so an external oscillator frequency of
24.705MHz would require an R
BIAS
resistance of no more
LTC6603
17
6603fa
APPLICATIONS INFORMATION
Figure 6. Current Controlled Clock Frequency
Figure 8. Voltage Controlled Clock Frequency
6603 F06
V+
IN
V+
A
V
OCM
R
BIAS
CLKCNTL
LPF1(CS)
+INB
–INB
LPF0(SCLK)
SDI
SDO
–OUTB
+INA
–INA
GAIN1
GAIN0(D0)
V
OCM
CAP
+OUTA
–OUTA
SER
V+
D
CLK IO
GND
+OUTB
LTC6603
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
C1
100nF
C2
2.2µF
C4
100nF
C3
2.2µF
C19
50pF
C18
50pF
C15
10nF
+OUTA
–OUTA
+OUTB
–OUTB
R23
50k
R24
50k
–INB +INB
R25
50k
R26
50k
+INA –INA
C17
50pF
C16
50pF
–IN
+IN
5V
7
OUT
–IN
+IN
OUT
R1
30.5k
5V
C7
100nF
V+
V–
2
3
SDO
SDI
SCK
CLR
CS/LD
LDAC
5V
C8
100nF
R4
100k
5V
7
1
2
3
4
5
10
C9
F
V
OUT
V
REF
V
CC
GND
LTC2621-1
SDI
SCLK
CS
5V 3V
I RANGE = 6µA TO 38.4µA
USE NARROW SHORT
TRACES FOR MINIMUM
CAPACITANCE.
Q1
RK7002AT116CT
21
LTC6078
LTC6078
CLR LOW WILL SET DAC TO MID-SCALE (WITH A LTC6603-1 VERSION).
HAS ~100ms TC AT START-UP TO RESET TO ZERO-SCALE.
DATA FORMAT
DATA IS SHIFTED FROM MOSI (MASTER OUT, SLAVE IN) THRU LTC6603 INTO THE LTC2621.
THE TOTAL PACKET IS 32 BITS. IT STARTS WITH A CONTROL BYTE (0011 XXXX) THEN MSB OF THE DAC,
WITH DUMMY BITS AT THE END, 16 BITS (24 BITS TOTAL). THEN 8 BITS TO THE FILTER.
D6 AND D7 = GAIN, D4 AND D5 = LPF, D1 = SHDN. D0 = GEN. PURPOSE OUTPUT.
SPI INTERFACE
V
OCM
V+
V–
V+
V+
IN
R
BIAS
6603 F08
V
CONTROL
f
CLK
= 247.2MHz • (10k/R
BIAS
) • (1 – V
CONTROL
/1.17V)
R
BIAS
+
FREQUENCY (Hz)
GAIN (dB)
6603 F07
10
0
–10
–20
–30
–40
–50
–60
–70
–80
1k 1M 10M100k10k
V
S
= 3V
T
A
= 25°C
Figure 7. Frequency Response Controlled by LTC2621-1
LTC6603
18
6603fa
APPLICATIONS INFORMATION
than 100k. If the value of R
BIAS
is too large, the fi lters will
not receive a large enough bias current, possibly causing
errors due to insuffi cient settling. Be sure to obey the
absolute maximum specifi cations when driving a clock
into CLKIO (Pin 15).
Input Common Mode and Differential Voltage Range
The input signal range extends from zero to the V+
IN
supply voltage. This input supply can be tied to V+
A
and
V+
D
, or driven up to 5.5V for increased input signal range.
Figure 9 shows the distortion of the fi lter versus common
mode input voltage with a 2V
P-P
differential input signal
(V+
IN
= 5V).
control bits LPF1 and LPF0. The differential input imped-
ance is a function of the clock frequency and the control
bits LPF1, LPF0, GAIN1 and GAIN0. Table 5 shows the
typical input impedances for a clock frequency of 80MHz.
These input impedances are all proportional to 1/f
CLK
, so
if the clock frequency were reduced by half to 40MHz,
the impedances would be doubled. The typical variation
in dynamic input impedance for a given clock frequency
is –20% to +35%.
Table 5. Differential, Common Mode Input Impedances,
f
CLK
= 80MHz
GAIN1 GAIN0 LPF1 LPF0
DIFFERENTIAL
INPUT IMPEDANCE
(k)
COMMON MODE
INPUT IMPEDANCE
(k)
0000 38 40
0001 16 20
0010 2.5 5
0011 2.5 5
0100 20 40
0101 9.5 20
0 1 1 0 2.5 5
0 1 1 1 2.5 5
1 0 0 0 10 40
1 0 0 1 5.4 20
1010 1.9 5
1011 1.9 5
1 1 0 0 5.2 40
1 1 0 1 2.8 20
1110 1.6 5
1111 1.6 5
Output Common Mode and Differential Voltage Range
The output voltage is a fully differential signal with a
common mode level equal to the voltage at V
OCM
. Any of
the fi lter outputs may be used as single-ended outputs,
although this will degrade the performance. The output
voltage range is typically 0.5V to V+
A
– 0.5V (V+
A
= 2.7V
to 3.6V).
The common mode output voltage can be adjusted by
overdriving the voltage present on V
OCM
. To maximize
the undistorted peak-to-peak signal swing of the fi lter,
the V
OCM
voltage should be set to V+
A
/2. Note that the
output common mode voltages of the two channels are
Figure 9. Distortion vs Common Mode Input Voltage (5V)
COMMON MODE INPUT VOLTAGE (V)
1.0
DISTORTION (dBc)
–60
–70
–80
–90
3.02.0 4.0
6603 F09
5.02.5 4.51.5 3.5
R
BIAS
= 30.9k, V
S
= 3V, V+
IN
= 5.5V
LPF1 = 1, BW = 2.5MHz, GAIN = 24dB
V
OUT
= V
P-P
, T
A
= 25°C
HD3, f = 1MHz
HD3, f = 200kHz
For best performance, the inputs should be driven dif-
ferentially. For single-ended signals, connect the unused
input to V
OCM
(Pin 3) or to a quiet DC reference voltage.
To achieve the best distortion performance, the input
signal should be centered around the DC voltage of the
unused input.
Refer to the Typical Performance Characteristics section
to estimate the distortion for a given input level.
Dynamic Input Impedance
The unique input sampling structure of the LTC6603
has a dynamic input impedance which depends on the
confi guration and the clock frequency. This dynamic
input impedance has both a differential component and
a common mode component. The common mode input
impedance is a function of the clock frequency and the

LTC6603CUF#PBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Active Filter Dual Programmable 2.5MHz Filter for Communications
Lifecycle:
New from this manufacturer.
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