LTC6603
21
6603fa
APPLICATIONS INFORMATION
results in four matched fi lter channels, all synchronized to
the same clock. The master has its CLKCNTL pin pulled
to V+
D
, confi guring its CLKIO pin as an output, while the
slave has its CLKCNTL pin pulled to ground, confi guring its
CLKIO pin as an input. Note that in order to synchronize the
two fi lters, the clock frequency must not be buffered. This
requires that the fi lters be close together on the PC board.
If the clock is buffered, the fi lters would have matching
bandwidths, but would not be synchronized.
Output Drive
The fi lter outputs can drive 1k and/or 50pF loads connected
to AC ground with a 0.5V to 2.5V signal (corresponding
to a 4V
P-P
differential signal). For differential loads (loads
connected between +OUTA and –OUTA or +OUTB and
–OUTB) the outputs can produce a 4V
P-P
signal across 2k
and/or 25pF. For smaller signal amplitudes, the outputs can
drive correspondingly larger loads. For larger capacitive
loads, an external 50 series resistor is recommended
for each output.
Clock Feedthrough
Clock feedthrough is defi ned as the RMS value of the clock
frequency and its harmonics that are present at the fi lter’s
output. The clock feedthrough is measured with +INA and
–INA (or +INB, –INB) tied to V
OCM
and depends on the PC
board layout and the power supply decoupling. The clock
feedthrough can be reduced with a simple RC post fi lter.
Decoupling Capacitors
The LTC6603 uses sampling techniques, therefore its
performance is sensitive to supply noise. 0.1µF ceramic
decoupling capacitors must be connected from V+
A
(Pin 2)
and V+
D
(Pin 16) to ground with leads as short as possible.
A ground plane should be used. Noisy signals should be
isolated from the fi lter’s input pins. In addition, a 0.1µF
decoupling capacitor at Pin 20 is recommended since this
pin receives clocked current injection.
Aliasing
Aliasing is an inherent phenomenon of sampled data fi lters.
Signifi cant aliasing only occurs when the frequency of
the input signal approaches the sampling frequency or
multiples of the sampling frequency. The ratio of the
LTC6603 input sampling frequency to the clock frequency,
f
CLK
, is determined by the state of control bits LPF1 and
LPF0. Table 6 shows the possible input sampling frequen-
cies for a clock frequency of 80MHz. The input sampling
frequency is proportional to the clock frequency. For
example, if the clock frequency is lowered from 80MHz
to 40MHz, the input sampling frequency will be lowered
by half. Input signals with frequencies near the input
sampling frequency will be aliased to the passband of
the fi lter and appear at the output unattenuated.
Table 6. Input Sampling Frequency (f
CLK
= 80MHz)
LPF1 LPF0 Input Sampling Frequency (MHz)
00 20
01 40
1 0 160
1 1 160
A simple LC anti-aliasing fi lter is recommended at the
fi lter inputs to attenuate frequencies near the input sam-
pling frequency that will be aliased to the passband. For
example, if the clock frequency is set to 80MHz and the
cutoff frequency of the fi lter is set to its maximum (LPF1
= 1), the lowest frequency that would be aliased to the
passband would be f
CLK
– f
CUTOFF
, i.e., 160MHz – 2.5MHz
= 157.5MHz. The LTC6603 fi lter inputs should be driven
by a low impedance output (<100).
Wideband Noise
The wideband noise of the fi lter is the RMS value of the
device’s output noise spectral density. The wideband noise
is nearly independent of the value of the clock frequency
and excludes the clock feedthrough. Most of the wideband
noise is concentrated in the fi lter passband and cannot be
removed with post fi ltering.
Power Supply Current
The power supply current depends on the state of the
lowpass cutoff frequency controls (LPF1, LPF0) and the
value of R
BIAS
. When the LTC6603 is programmed for the
middle cutoff frequency (LPF1 = 0, LPF0 = 1), the supply
current is reduced by about 23% relative to the supply
current for the higher bandwidth setting. Programming
