74ALVCH16827DGGS

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74ALVCH16827
20-bit buffer/line driver, non-inverting
(3-State)
Product specification
IC24 Data Handbook
1998 Jul 27
INTEGRATED CIRCUITS
Philips Semiconductors Product specification
74ALVCH1682720-bit buffer/line driver, non-inverting (3-State)
2
1998 Jul 27 853-2096 19785
FEATURES
Wide supply voltage range of 1.2V to 3.6V
Complies with JEDEC standard no. 8-1A
Wide supply voltage range of 1.2V to 3.6V
CMOS low power consumption
Direct interface with TTL levels
Universal bus transceiver with D-type latches and D-type flip-flops
capable of operating in transparent, latched, clocked or
clocked-enabled mode.
MULTIBYTE
TM
flow-through standard pin-out architecture
Low inductance multiple V
CC
and GND pins for minimum noise
and ground bounce
Current drive ±24 mA at 3.0 V
All inputs have bus hold circuitry
Output drive capability 50 transmission lines @ 85°C
3-State non-inverting outputs for bus oriented applications
DESCRIPTION
The 74ALVCH16827 is a 20-bit non-inverting buffer/driver with
3-State outputs for bus oriented applications.
The 74ALVCH16827 consists of two 10-bit sections with separate
output enable signals. For either 10-bit buffer section, the two output
enable (1OE
1 and 1OE2 or 2OE1 and 2OE2) inputs must both be
active. If either output enable input is high, the outputs of that 10-bit
buffer section are in high impedance state.
The 74ALVCH16827 has active bus hold circuitry which is provided
to hold unused or floating data inputs at a valid logic level. This
feature eliminates the need for external pull-up or pull-down
resistors.
QUICK REFERENCE DATA
GND = 0V; T
amb
= 25°C; t
r
= t
f
= 2.5ns
SYMBOL
PARAMETER CONDITIONS TYPICAL UNIT
t
PHL
/t
PLH
Propagation delay
CP to Qn
V
CC
= 2.5V, C
L
= 30pF
V
CC
= 3.3V, C
L
= 50pF
2.0
2.0
ns
C
I
Input capacitance 5 pF
C
PD
Power dissi
p
ation ca
p
acitance
p
er latch
V
I
= GND to V
CC
1
Output enabled 20
p
F
C
PD
Power
dissi ation
ca acitance
er
latch
V
I
=
GND
to
V
CC
1
Output disabled 3
F
NOTES:
1. C
PD
is used to determine the dynamic power dissipation (P
D
in W):
P
D
= C
PD
× V
CC
2
× f
i
+ (C
L
× V
CC
2
× f
o
) where:
f
i
= input frequency in MHz; C
L
= output load capacity in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V;
(C
L
× V
CC
2
× f
o
) = sum of outputs.
ORDERING INFORMATION
PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER
56-Pin Plastic TSSOP Type II –40°C to +85°C 74ALVCH16827 DGG ACH16827 DGG SOT364-1
PIN DESCRIPTION
PIN NUMBER SYMBOL FUNCTION
55, 54, 52, 51, 49, 48, 47, 45, 44, 43,
42, 41, 40, 38, 37, 36, 34, 33, 31, 30
1A0 - 1A9
2A0 - 2A9
Data inputs
2, 3, 5, 6, 8, 9, 10, 12, 13, 14,
15, 16, 17, 19, 20, 21, 23, 24, 26, 27
1Y0 - 1Y9
2Y0 - 2Y9
Data outputs
1, 56,
28, 29
1OE0, 1OE1
2OE0, 2OE1
Output enable inputs (active-Low)
4, 11, 18, 25, 32, 39, 46, 53 GND Ground (0V)
7, 22, 35, 50 V
CC
Positive supply voltage

74ALVCH16827DGGS

Mfr. #:
Manufacturer:
Nexperia
Description:
Buffers & Line Drivers 20-Bit Buffer/Line Driver non-Inverting
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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