MAX5066
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
______________________________________________________________________________________ 19
load step. Use a combination of SP polymer and
ceramic capacitors for better transient load and rip-
ple/noise performance.
Keep the maximum output-voltage deviation less than
or equal to the adaptive voltage-positioning window
(V
OUT
). During a load step, assume a 50% contribu-
tion each from the output capacitance discharge and
the voltage drop across the ESR (V
OUT
= V
ESR_
OUT
+ V
Q_OUT
). Use the following equations to calculate
the required ESR and capacitance value:
where I
LOAD_STEP
is the step in load current and
t
RESPONSE
is the response time of the controller.
Controller response time depends on the control-loop
bandwidth. C
OUT
is C6 and C7 in Figure 6.
Current Limit
The average current-mode control technique of the
MAX5066 accurately limits the maximum average out-
put current per phase. The MAX5066 senses the volt-
age across the sense resistor and limits the maximum
inductor current accordingly. Use the equations below
to calculate the current-sense resistor values:
Due to tolerances involved, the minimum average volt-
age at which the voltage across the current-sense
resistor is clamped is 20.4mV. Therefore, the minimum
average current limit is set at:
For example, the current-sense resistor:
for a maximum output current of 10A. The standard
value is 2m. Also, adjust the value of the current-
sense resistor to compensate for parasitics associated
with the PC board. Select a noninductive resistor with
appropriate wattage rating.
The second type of current limit is the peak current limit
as explained in the Peak-Current Comparator section.
The third current-protection circuit is the hiccup fault
protection as explained in the Hiccup Fault Protection
section. The average current during a short at the out-
put is given by:
Reverse Current Limit
The MAX5066 limits the reverse current when the output
capacitor voltage is higher than the preset output volt-
age. Calculate the maximum reverse current limit based
on V
CLAMP_LO
and the current-sense resistor R
SENSE
.
I
R
AVG SHORT
SENSE
()
.
=
×
141 10
3
R
mV
A
m
SENSE
==
20 4
10
204
.
.
I
R
LIMIT MIN
SENSE
()
.
=
×
20 4 10
3
I
R
LOAD MAX
SENSE
()
.
=
×
24 75 10
3
R
V
I
C
It
V
ESR OUT
ESR OUT
LOAD STEP
OUT
LOAD STEP RESPONSE
Q OUT
_
_
_
_
_
=
=
×
LOSS DESCRIPTION SEGMENT LOSSES
Conduction Loss
Losses associated with MOSFET on-time, I
RMS
is a function of load current and duty cycle.
Gate Drive Loss
Losses associated with charging and
discharging the gate of the MOSFET every
cycle. There is no Q
GD
charging involved in this
MOSFET due to the zero-voltage turn-on. The
charge involved is (Q
G
- Q
GD
).
Table 2. Low-Side MOSFET Losses
PIR
where I
VV
V
I
CONDUCTION RMS DS ON
RMS
IN OUT
IN
LOAD
×
2
()
PVQQf
GATEDRIVE DD G GD SW
×()
Note: The gate drive losses are distributed between the drivers and the MOSFETs in the ratio of the gate driver’s resistance and the
MOSFET’s internal gate resistance.
MAX5066
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
20 ______________________________________________________________________________________
Output-Voltage Setting
The output voltage is set by the combination of resistors
R1, R2, and R
F
as described in the Voltage Error Amplifier
section. First select a value for resistor R2. Then calculate
the value of R1 from the following equation:
where V
OUT(NL)
is the voltage at no load. Then find the
value of R
F
from the following equation:
where V
OUT
is the allowable drop in voltage from no
load to full load. R
F
is R8 and R9, R1 is R4 and R6, R2
is R5 and R7 in Figure 6.
Compensation
The MAX5066 uses an average current-mode control
scheme to regulate the output voltage (see Figure 2).
The main control loop consists of an inner current loop
and an outer voltage loop. The voltage error amplifier
(VEA1 and VEA2) provides the controlling voltage for
the current loop in each phase. The output inductor is
“hidden” inside the inner current loop. This simplifies
the design of the outer voltage control loop and also
improves the power-supply dynamics. The objective of
the inner current loop is to control the average inductor
current. The gain-bandwidth characteristic of the cur-
rent loop can be tailored for optimum performance by
the compensation network at the output of the current-
error amplifier (CEA1 or CEA2). Compared with peak
current-mode control, the current-loop gain crossover
frequency, f
C
, can be made approximately the same,
but the gain at low frequencies is much higher. This
results in the following advantages over peak current-
mode control.
1) The average current tracks the programmed cur-
rent with a high degree of accuracy.
2) Slope compensation is not required, but there is a
limit to the loop gain at the switching frequency in
order to achieve stability.
3) Noise immunity is excellent.
4) The average current-mode method can be used to
sense and control the current in any circuit branch.
For stability of the current loop, the amplified inductor-
current downslope at the negative input of the PWM
comparator (CPWM1 and CPWM2) must not exceed
the ramp slope at the comparator’s positive input. This
puts an upper limit on the current-error amplifier gain at
the switching frequency. The inductor current downs-
lope is given by V
OUT
/L where L is the value of the
inductor (L1 and L2 in Figure 6) and V
OUT
is the output
voltage. The amplified inductor current downslope at
the negative input of the PWM comparator is given by:
where R
SENSE
is the current-sense resistor (R1 and R2
in Figure 6) and g
M
x R
CF
is the gain of the current-error
amplifier (CEA_) at the switching frequency. The slope
of the ramp at the positive input of the PWM comparator
is 2V x f
SW
. Use the following equation to calculate the
maximum value of R
CF
(R14 or R15 in Figure 6).
The highest crossover frequency f
CMAX
is given by:
or alternatively:
Equation (1) can now be rewritten as:
In practical applications, pick the crossover frequency
(f
C
) in the range of:
First calculate R
CF
in equation 2 above. Calculate C
CF
such that:
where C
CF
is C10 and C12 in Figure 6.
C
fR
CF
CCF
=
×× ×
10
2 π
f
f
f
SW
C
SW
10 2
<< .
R
fL
VR g
CF
C
IN S M
=
××
×××
π
9
2()
f
fV
V
SW
CMAX OUT
IN
=
××2π
f
fV
V
CMAX
SW IN
OUT
=
×
×2π
R
fL
VR g
CF
SW
OUT SENSE M
××
×××
2
36
1()
V
t
V
L
RgR
L OUT
SENSE M CF
×××36
R
IR R
V
F
OUT SENSE
OUT
=
×××36
1
R
V
R
OUT NL
1
0 6135
0 6135
2
(.)
.
()
=
×
I
R
REVERSE
SENSE
=
×
163 10
3
.
MAX5066
Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
______________________________________________________________________________________ 21
Calculate C
CFF
such that:
where C
CFF
is C11 and C13 in Figure 6.
Applications Information
Independant Turn-On and Off
The MAX5066 can be used to regulate two outputs
from one controller. Each of the two outputs can be
turned on and off independently of one another by con-
trolling the enable input of each phase (EN1 and EN2).
A logic-low on each enable pin shuts down the
MOSFET drivers for that phase. When the voltage on
the enable pin exceeds 1.2V, the drivers are turned on
and the output can come up to regulation. This method
of turning on the outputs allows the MAX5066 to be
used for power sequencing.
PC Board Layout Guidelines
Careful PC board layout is critical to achieve low loss-
es, low output noise, and clean and stable operation.
This is especially true for dual-phase converters where
one channel can affect the other. Use the following
guidelines for PC board layout:
1) Place the V
DD
, REG, and the BST1 and BST2
bypass capacitors close to the MAX5066.
2) Minimize all high-current switching loops.
3) Keep the power traces and load connections short.
This practice is essential for high efficiency. Use
thick copper PC boards (2oz or higher) to enhance
efficiency and minimize trace inductance and
resistance.
4) Run the current-sense lines CSP_ and CSN_ very
close to each other to minimize loop areas. Do not
cross these critical signal lines through power cir-
cuitry. Sense the current right at the pads of the
current-sense resistors.
5) Place the bank of output capacitors close to the
load.
6) Isolate the power components on the top side from
the analog components on the bottom side with a
ground plane in between.
7) Provide enough copper area around the switching
MOSFETs, inductors, and sense resistors to aid in
thermal dissipation and reducing resistance.
8) Distribute the power components evenly across the
top side for proper heat dissipation.
9) Keep AGND and PGND isolated and connect them
at one single point close to the IC. Do not connect
them together anywhere else.
10) Place all input bypass capacitors for each input as
close to each other as is practical.
C
fR
CFF
CCF
=
×× × ×
1
210π
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
EN2
BST2
DH2
LX2
DL2
PGND
EN1
IN
REG
V
DD
DL1
LX1
DH1
BST1
CSN1
CSP1
EAOUT1
EAN1
CLP1
MODE
AGND
RT/CLKIN
REF
CLP2
EAN2
EAOUT2
CSP2
CSN2
TSSOP
TOP VIEW
MAX5066
*EXPOSED PADDLE
*CONNECT EXPOSED PAD TO GROUND PLANE.
Pin Configuration
Chip Information
TRANSISTOR COUNT: 6252
PROCESS: BiCMOS

MAX5066EUI+T

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Switching Controllers Synch Buck Controller
Lifecycle:
New from this manufacturer.
Delivery:
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