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LT1425IS#TRPBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
13
LT1425
APPLICATIONS INFORMATION
WUU
U
degrades load regulation (at least before load compensa-
tion is employed).
Bifilar Winding
A bifilar or similar winding technique is a good way to
minimize troublesome leakage inductances. However,
remember that this will increase primary-to-secondary
capacitance and limit the primary-to-secondary break-
down voltage, so bifilar winding is not always practical.
Finally, the LTC Applications group is available to assist
in the choice and/or design of the transformer. Happy
Winding!
OUTPUT VOLTAGE ERROR SOURCES
Conventional nonisolated switching power supply ICs
typically have only two substantial sources of output
voltage error—the internal or external resistor divider
network that connects to V
OUT
and the internal IC refer-
ence. The LT1425, which senses the output voltage in both
a dynamic and an isolated manner, exhibits additional
potential error sources to contend with. Some of these
errors are proportional to output voltage, others are fixed
in an absolute millivolt sense. Here is a list of possible
error sources and their effective contribution:
Internal Voltage Reference
The internal bandgap voltage reference is, of course,
imperfect. Its error, both at 25°C and over temperature is
already included in the specifications for Reference
Current.
User Programming Resistors
Output voltage is controlled by the ratio of R
FB
to R
REF
.
Both are user supplied external resistors. To the extent
that the resistor ratio differs from the ideal value, the
output voltage will be proportionally affected.
Schottky Diode Drop
The LT1425 senses the output voltage from the trans-
former primary side during the flyback portion of the cycle.
This sensed voltage therefore includes the forward drop,
V
F
, of the rectifier (usually a Schottky diode). The nominal
signal! It then reverts to a potentially stable state whereby
the top of the leakage spike is the control point, and the
trailing edge of the leakage spike triggers the collapse
detect circuitry. This will typically reduce the output volt-
age abruptly to a fraction, perhaps between one-third to
two-thirds of its correct value. If load current is reduced
sufficiently, the system will snap back to normal opera-
tion. When using transformers with considerable leakage
inductance, it is important to exercise this worst-case
check for potential bistability:
1. Operate the prototype supply at maximum expected
load current.
2. Temporarily short circuit the output.
3. Observe that normal operation is restored.
If the output voltage is found to hang up at an abnormally
low value, the system has a problem. This will usually be
evident by simultaneously monitoring the V
SW
waveform
on an oscilloscope to observe leakage spike behavior
firsthand. A final note, the susceptibility of the system to
bistable behavior is somewhat a function of the load I/V
characteristics. A load with resistive, i.e., I = V/R behavior
is the most susceptible to bistability. Loads which exhibit
“CMOSsy”, i.e., I = V
2
/R behavior are less susceptible.
Secondary Leakage Inductance
In addition to the previously described effects of leakage
inductance in general, leakage inductance on the second-
ary in particular exhibits an additional phenomenon. It
forms an inductive divider on the transformer secondary,
that reduces the size of the primary-referred flyback pulse
used for feedback. This will increase the output voltage
target by a similar percentage. Note that unlike leakage
spike
behavior, this phenomenon is load independent. To
the extent that the secondary leakage inductance is a
constant percentage of mutual inductance (over manufac-
turing variations), this can be accommodated by adjusting
the R
FB
/R
REF
resistor ratio.
Winding Resistance Effects
Resistance in either the primary or secondary will act to
reduce overall efficiency (P
OUT
/P
IN
). Resistance in the
secondary increases effective output impedance which
14
LT1425
APPLICATIONS INFORMATION
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“collapse,” thereby supporting operation well into discon-
tinuous mode. Nevertheless, there still remain constraints
to ultimate low load operation. They relate to the minimum
switch ON time and the minimum enable time. Discontinu-
ous mode operation will be assumed in the following
theoretical derivations.
As outlined in the Operation section, the LT1425 utilizes a
minimum output switch ON time, t
ON
. This value can be
combined with expected V
IN
and switching frequency to
yield an expression for minimum delivered power.
1
2
)
)
f
L
PRI
)
)
Min Power = (V
IN
• t
ON
)
2
= (V
OUT
)(I
OUT
)
This expression then yields a minimum output current
constraint:
1
2
)
)
f
(L
PRI
)(V
OUT
)
)
)
I
OUT(MIN)
=
where,
f = Switching frequency (nominally 285kHz)
L
PRI
= Transformer primary side inductance
V
IN
= Input voltage
V
OUT
= Output voltage
t
ON
= Output switch minimum ON time
(V
IN
• t
ON
)
2
An additional constraint has to do with the minimum
enable time. The LT1425 derives its output voltage infor-
mation from the flyback pulse. If the internal minimum
enable time pulse extends beyond the flyback pulse, loss
of regulation will occur. The onset of this condition can be
determined by setting the width of the flyback pulse equal
to the sum of the flyback enable delay, t
ED
, plus the
minimum enable time, t
EN
. Minimum power delivered to
the load is then:
1
2
)
)
f
L
SEC
)
)
Min Power =
[V
OUT
• (t
EN
+ t
ED
)]
2
= (V
OUT
)(I
OUT
)
which yields a minimum output constraint:
V
F
of this diode should therefore be included in R
FB
calculations. Lot-to-lot and ambient temperature varia-
tions will show up as output voltage shift/drift.
Secondary Leakage Inductance
Leakage inductance on the transformer secondary
reduces the effective primary-to-secondary turns ratio
(N
P
/N
S
) from its ideal value. This will increase the output
voltage target by a similar percentage. To the extent that
secondary leakage inductance is constant from part-to-
part, this can be accommodated by adjusting the R
FB
to
R
REF
resistor ratio.
Output Impedance Error
An additional error source is caused by transformer sec-
ondary current flow through the real life nonzero imped-
ances of the output rectifier, transformer secondary and
output capacitor. Because the secondary current only
flows during the off portion of the duty cycle, the effective
output impedance equals the “DC” lumped secondary
impedance times the inverse of the off duty cycle. If the
output load current remains relatively constant, or, in less
critical applications, the error may be judged acceptable
and the R
FB
value adjusted for nominal expected error. In
more demanding applications, output impedance error
may be minimized by the use of the load compensation
function (see Load Compensation).
V
IN
Sense Error
The LT1425 determines the size of the flyback pulse by
comparing the V
SW
signal to V
IN
, through R
FB
. This
comparison is not perfect, in the sense that an offset exists
between the sensing mechanism and the actual V
IN
. This
is expressed in the data sheet as V
IN
sense error. This error
is fixed in absolute millivolt terms relative to V
OUT
(with the
exception that it is reflected to V
OUT
by any nonunity
secondary-to-primary turns ratio).
MINIMUM LOAD CONSIDERATIONS
The LT1425 generally provides better low load perfor-
mance than previous generation switcher/controllers
utilizing indirect output voltage sensing techniques.
Specifically, it contains circuitry to detect flyback pulse
15
LT1425
APPLICATIONS INFORMATION
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minimum switch ON time, irrespective of current trip
point. If the duty cycle exhibited by this minimum ON time
is greater than the ratio of secondary winding voltage
(referred-to-primary) divided by input voltage, then peak
current will not be controlled at the nominal value, and will
cycle-by-cycle ratchet up to some higher level. Expressed
mathematically, the requirement to maintain short-circuit
control is:
V
F
+ (I
SC
)(R
SEC
)
(V
IN
)(N
SP
)
)
)
(t
ON
)(f) <
where,
t
ON
= Output switch minimum ON time
f = Switching frequency
I
SC
= Short-circuit output current
V
F
= Output diode forward voltage at I
SC
R
SEC
= Resistance of transformer secondary
V
IN
= Input voltage
N
SP
= Secondary-to-primary turns ratio
(N
SEC
/N
PRI
)
Trouble will typically only be encountered in applications
with a relatively high product of input voltage times
secondary-to-primary turns ratio. Additionally, several
real world effects such as transformer leakage inductance,
AC winding losses and output switch voltage drop com-
bine to make this simple theoretical calculation a conser-
vative estimate. In cases where short-circuit protection is
mandatory and this theoretical calculation indicates cause
for concern, the prototype should be observed directly as
follows: short the output while observing the V
SW
signal
with an oscilloscope. The measured output switch ON
time can then be compared against the specifications for
minimum t
ON
.
THERMAL CONSIDERATIONS
Care should be taken to ensure that the worst-case input
voltage and load current conditions do not cause exces-
sive die temperatures. The narrow 16-pin package is rated
at 75°C/W.
1
2
)
)
f(V
OUT
)
L
SEC
)
)
I
OUT(MIN)
=
where,
f = Switching frequency (nominally 285kHz)
L
SEC
= Transformer secondary side inductance
V
OUT
= Output voltage
t
ED
= Enable delay time
t
EN
= Minimum enable time
(t
ED
+ t
EN
)
2
Note that generally, depending on the particulars of input
and output voltages and transformer inductance, one of
the above constraints will prove more restrictive. In other
words, the minimum load current in a particular applica-
tion will be either “output switch minimum ON time”
constrained, or “minimum flyback pulse time” constrained.
(A final note—L
PRI
and L
SEC
refer to transformer induc-
tance as seen from the primary or secondary side respec-
tively. This general treatment allows these expressions to
be used when the transformer turns ratio is nonunity.)
MAXIMUM LOAD/SHORT-CIRCUIT CONSIDERATIONS
The LT1425 is a current mode controller. It uses the V
C
node voltage as an input to a current comparator which
turns off the output switch on a cycle-by-cycle basis as
this peak current is reached. The internal clamp on the V
C
node, nominally 1.9V, then acts as an output switch peak
current limit. This action becomes the switch current limit
specification. The maximum available output power is
then determined by the switch current limit, which is
somewhat duty cycle dependent due to internal slope
compensation action.
Short-circuit conditions are handled by the same mecha-
nism. The output switch turns on, peak current is quickly
reached and the switch is turned off. Because the output
switch is only on for a small fraction of the available period,
internal power dissipation is controlled. (The LT1425
contains an internal overtemperature shutdown circuit,
that disables switch action, just in case.)
While the majority of users will not experience a problem,
there is however, a possibility of loss of current limit under
certain conditions. Remember that the LT1425 exhibits a
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LT1425IS#TRPBF

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Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators Isolated Flyback DC/DC Converter
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