DATASHEET
LOCO™ PLL CLOCK MULTIPLIER ICS511
IDT™ / ICS™
LOCO™ PLL CLOCK MULTIPLIER 1
ICS511 REV J 092209
Description
The ICS511 LOCO
TM
is the most cost effective way to
generate a high quality, high frequency clock output
from a lower frequency crystal or clock input. The name
LOCO stands for Low Cost Oscillator, as it is designed
to replace crystal oscillators in most electronic
systems. Using Phase-Locked Loop (PLL) techniques,
the device uses a standard fundamental mode,
inexpensive crystal to produce output clocks up to 200
MHz.
Stored in the chip’s ROM is the ability to generate nine
different multiplication factors, allowing one chip to
output many common frequencies (see table on page
2).
The device also has an output enable pin which
tri-states the clock output when the OE pin is taken low.
This product is intended for clock generation. It has low
output jitter (variation in the output period), but input to
output skew and jitter are not defined nor guaranteed.
For applications which require defined input to output
skew, use the ICS570B.
Features
Packaged as 8-pin SOIC or die
Available in Pb (lead) free package
Upgrade of popular ICS501 with:
- changed multiplier table
- faster operating frequencies
- output duty cycle at VDD/2
Zero ppm multiplication error
Input crystal frequency of 5 - 27 MHz
Input clock frequency of 2 - 50 MHz
Output clock frequencies up to 200 MHz
Extremely low jitter of 25 ps (one sigma)
Compatible with all popular CPUs
Duty cycle of 45/55 up to 200 MHz
Mask option for nine selectable frequencies
Operating voltage of 3.3 V or 5 V
Tri-state output for board level testing
Industrial temperature version available
Advanced, low power CMOS process
NOTE: EOL for non-green parts to occur on
5/13/10 per PDN U-09-01
Block Diagram
CLK
PLL Clock
Multiplier
Circuitry
and ROM
Crystal or
Clock input
GND
OE
VDD
Crystal
Oscillator
S1:0
X1/ICLK
X2
Optional crystal capacitors
2
ICS511
LOCO™ PLL CLOCK MULTIPLIER CLOCK MULTIPLIER
IDT™ / ICS™
LOCO™ PLL CLOCK MULTIPLIER 2
ICS511 REV J 092209
Pin Assignment Clock Output Table
0 = connect directly to ground
1 = connect directly to VDD
M = leave unconnected (floating)
Common Output Frequency Examples (MHz)
Pin Descriptions
X1/ICLK
VDD
GND
OE
S1
S0
CLK
X21
2
3
4
8
7
6
5
8 Pin (150 mil) SOIC
S1 S0 CLK
0 0 4X input
0 M 5.333X input
0 1 5X input
M 0 2.5X input
M M 2X input
M 1 3.333X input
1 0 6X input
1 M 3X input
1 1 8X input
Output 20 24 30 32 33.33 37.5 40 48 50 60 64
Input 10 12 10 16 16.66 15 10 12 20 10 16
Selection (S1, S0) M, M M, M 1, M M, M M, M M, 0 0, 0 0, 0 M, 0 1, 0 0, 0
Output 66.66 72 75 80 83.33 90 100 120 125 133.3 150
Input 20 12 25 10 25 15 20 15 25 25 25
Selection (S1, S0) M, 1 1, 0 1, M 1, 1 M, 1 1, 0 0, 1 1, 1 0, 1 0, M 1, 0
Pin
Number
Pin
Name
Pin
Type
Pin Description
1 XI/ICLK Input Crystal connection or clock input.
2 VDD Power Connect to +3.3 V or +5 V.
3 GND Power Connect to ground.
4 S1 Tri-level Iinput Select 1 for output clock. Connect to GND or VDD or float.
5 CLK Output Clock output per table above.
ICS511
LOCO™ PLL CLOCK MULTIPLIER CLOCK MULTIPLIER
IDT™ / ICS™
LOCO™ PLL CLOCK MULTIPLIER 3
ICS511 REV J 092209
External Components
Decoupling Capacitor
As with any high-performance mixed-signal IC, the
ICS511 must be isolated from system power supply
noise to perform optimally.
A decoupling capacitor of 0.01µF must be connected
between VDD and the GND. It must be connected close
to the ICS511 to minimize lead inductance. No external
power supply filtering is required for the ICS511.
Series Termination Resistor
A 33 terminating resistor can be used next to the CLK
pin for trace lengths over one inch.
Crystal Load Capacitors
The total on-chip capacitance is approximately 12 pF. A
parallel resonant, fundamental mode crystal should be
used. The device crystal connections should include
pads for small capacitors from X1 to ground and from
X2 to ground. These capacitors are used to adjust the
stray capacitance of the board to match the nominally
required crystal load capacitance. Because load
capacitance can only be increased in this trimming
process, it is important to keep stray capacitance to a
minimum by using very short PCB traces (and no vias)
between the crystal and device. Crystal capacitors, if
needed, must be connected from each of the pins X1
and X2 to ground.
The value (in pF) of these crystal caps should equal (C
L
-12 pF)*2. In this equation, C
L
= crystal load capacitance
in pF. Example: For a crystal with a 16 pF load
capacitance, each crystal capacitor would be 8 pF
[(16-12) x 2] = 8.
6 S0 Tri-level Input Select 0 for output clock. Connect to GND or VDD or float.
7 OE Input Output enable. Tri-states CLK output when low. Internal pull-up
resistor.
8 X2 Output Crystal connection. Leave unconnected for clock input.
Pin
Number
Pin
Name
Pin
Type
Pin Description

ICS511MI

Mfr. #:
Manufacturer:
Description:
IC PLL CLOCK MULTIPLIER 8-SOIC
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet