13
LT1339
sn1339 1339fas
APPLICATIONS INFORMATION
WUU
U
Subharmonic oscillations can be eliminated by augment-
ing the increasing ripple current slope (S1) in the control
loop. This is accomplished by adding an artificial ramp on
the inductor current waveform internal to the IC (with a
slope S
X
) as shown in Figure 5b. If the sum of the slopes
S1 + S
X
is greater than S2, the condition for subharmonic
oscillation no longer exists.
For a buck converter, the required additional current wave-
form slope, or “Slope Compensation,” follows the relation:
S
V
L
DC
X
IN
()
21
For duty cycles less than 50% (DC < 0.5), S
X
is negative
and is not required. For duty cycles greater than 50%, S
X
takes on values dependent on S1 and duty cycle. This leads
to a minimum inductance requirement for a given V
IN
and
duty cycle of:
L
V
S
DC
MIN
IN
X
=
()
21
The LT1339 contains an internal S
X
slope compensation
ramp that has an equivalent current referred value of:
0.084
f
R
O
SENSE
Amp/s
where f
O
is oscillator frequency. This yields a minimum
inductance requirement of:
L
VR DC
f
MIN
IN SENSE
O
()( )
()
()()
21
0 084.
A down side of slope compensation is that, since the IC servo
loop senses an increase in perceived inductor current, the
internal current limit functions are affected such that the
maximum current capability of a regulator is reduced by the
same amount as the effective current referred slope com-
pensation. The LT1339, however, uses a current limit
scheme that is independent of slope compensation effects
(average current limit). This provides operation at any duty
cycle with no reduction in current sourcing capability,
provided ripple current peak amplitude is less than 15% of
the current limit value. For example, if the supply is set up
to current limit at 10A, as long as the peak inductor current
is less than 11.5A, duty cycles up to 90% can be achieved
without compromising the average current limit value.
If an inductor smaller than the minimum required for
internal slope compensation (calculated above as L
MIN
) is
desired, additional slope compensation is required. The
LT1339 provides this capability through the SL/ADJ pin.
This feature is implemented by referencing this pin via a
resistor divider from the 5V
REF
pin to ground. The addi-
tional slope compensation will be affected at the point in
the oscillator waveform (at pin CT) corresponding to the
voltage set by the resistor divider. Additional slope com-
pensation can be calculated using the relation:
S
f
RR
XADD
O
EQ SENSE
=
()()
()( )
2500
Amp/s
where R
EQ
is the effective resistance of the resistor divider.
Actual compensation will be somewhat greater due to in-
ternal curvature correction circuitry that imposes an expo-
nential increase in the slope compensation waveform,
OSCILLATOR
PERIOD
TIME
0 0
ab
I
T1
I
2
I
1
S1 S1S2 S2
S1 + S
X
1339 • F05
Figure 5. Inductor Current at DC > 50% and
Slope Compensation Adjusted Signal
DUTY CYCLE (DC)
0
PEAK/AVG
0.4
1.45
1.40
1.35
1.30
1.25
1.20
1.15
1.10
LT1339 • F06
0.2 0.6
0.1
0.5
0.3 0.7 0.8 0.9
Figure 6. Maximum Ripple Current (Normalized)
vs Duty Cycle for Average Current Limit
14
LT1339
sn1339 1339fas
APPLICATIONS INFORMATION
WUU
U
Selection criteria for the power MOSFETs include the “ON”
resistance (R
DS(ON)
), reverse transfer capacitance (C
RSS
),
maximum drain-source voltage (V
DSS
) and maximum
output current.
The power FETs selected must have a maximum operating
V
DSS
exceeding the maximum V
IN
. V
GS
voltage maximum
must exceed the 12V
IN
supply voltage.
Once voltage requirements have been determined, R
DS(ON)
can be selected based on allowable power dissipation and
required output current.
In an LT1339 buck converter, the average inductor current
is equal to the DC load current. The average currents
through the main and synchronous switches are:
I
MAIN
= (I
LOAD
)(DC)
I
SYNC
= (I
LOAD
)(1 – DC)
The R
DS(ON)
required for a given conduction loss can be
calculated using the relation:
P
LOSS
= (I
SWITCH
)
2
(R
DS(ON)
)
further increasing the effective compensation slope up to
20% for a given setting.
Design Example:
V
IN
= 20V
V
OUT
= 15V (DC = 0.75)
R
SENSE
= 0.01
f
O
= 100kHz
L = 5µH
The minimum inductor usable with no additional slope
compensation is:
L
V
H
MIN
()
()
()
()( )
20 0 01 1 5 1
0 084 100000
11 9
..
.
.
Since L = 5µH is less than L
MIN
, additional slope compen-
sation is necessary. The total slope compensation
required is:
S
V
H
X
µ
()
=
()
20
5
15 1 2 10
6
.
Amp/s
Subtracting the internally generated slope compensation
and solving for the required effective resistance at SL/ADJ
yields:
R
f
Rf
k
EQ
O
SENSE O
()()
()
()
()()
=
2500
2 10 0 084
21 5
6
.
.
Setting the resistor divider reference voltage at 2V assures
that the additional compensation waveform will be
enabled at 75% duty cycle. As shown in Figure 7a, using
R
SL1
= 45k and R
SL2
= 30k sets the desired reference
voltage and has a R
EQ
of 18k, which meets both design
requirements. Figure 7b shows the slope compensation
effective waveforms both with and without the SL/ADJ
external resistors.
Power MOSFET and Catch Diode Selection
External N-channel MOSFET switches are used with the
LT1339. The positive gate-source drive voltage of the
LT1339 for both switches is roughly equivalent to the
12V
IN
supply voltage, so standard threshold MOSFETs
can be used.
R
SL2
30k
R
SL1
45k
1339 • F07a
5V
REF
LT1339
2
SL/ADJ
4
Figure 7a. External Slope Compensation Resistors
Figure 7b. Slope Compensation Waveforms
(0.084 + 0.139)(f
O
)
R
SENSE
(0.084)(f
O
)
R
SENSE
2.5V
2V
0.8V
DC = 0.75
1339 • F07b
15
LT1339
sn1339 1339fas
APPLICATIONS INFORMATION
WUU
U
2000 hours (three months) lifetime; it is advisable to
derate either the ESR or temperature rating of the capaci-
tor for increased MTBF of the regulator.
The output capacitor in a buck converter generally has
much less ripple current than the input capacitor. Peak-to-
peak ripple current is equal to that in the inductor (I
L
),
typically a fraction of the load current. C
OUT
is selected to
reduce output voltage ripple to a desirable value given an
expected output ripple current. Output ripple (V
OUT
) is
approximated by:
V
OUT
I
L
{ESR + [(4)(f
O
)
C
OUT
]
–1
}
where f
O
= operating frequency.
Efficiency Considerations and Heat Dissipation
High output power applications have inherent concerns
regarding power dissipation in converter components.
Although high efficiencies are achieved using the LT1339,
the power dissipated in the converter climbs to relatively
high values when the load draws large amounts of power.
Even at 90% efficiency, an application that provides 500W
to the load has conversion loss of 55W.
I
2
R dissipation through the switches, sense resistor and
inductor series resistance create substantial losses under
high currents. Generally, the dominant I
2
R loss is evident
in the FET switches. Loss in each switch is proportional to
the conduction time of that switch. For example, in a 48V
to 5V converter the synchronous FET conducts load cur-
rent for almost 90% of the cycle time and thus, requires
greater consideration for dissipating I
2
R power.
Gate charge/discharge current creates additional current
drain on the 12V supply. If powered from a high voltage
input through a linear regulator, the losses in that regula-
tor device can become significant. A supply solution
bootstrapped from the output would draw current from a
lower voltage source and reduce this loss component.
Transition losses are significant in the topside switch FET
when high V
IN
voltages are used. Transition losses can be
estimated as:
P
TLOSS
2(V
IN
)
2
(I
MAX
)(C
RSS
)(f
O
)
Since the conduction time in the main switch of a 48V to
5V converter is small, the I
2
R loss in the main switch FET
In high voltage applications (V
IN
> 20V), the topside switch
is required to slew very large voltages. As V
IN
increases,
transition losses increase through a square relation, until
it becomes the dominant power loss term in the main
switch. This transition loss takes the form:
P
TR
(k)(V
IN
)
2
(I
MAX
)(C
RSS
)(f
O
)
where k is a constant inversely related to the gate drive
current, approximated by k = 2 in LT1339 applications.
The maximum power loss terms for the switches are thus:
P
MAIN
= (DC)(I
MAX
)
2
(1 + δ)(R
DS(ON)
) +
2(V
IN
)
2
(I
MAX
)(C
RSS
)(f
O
)
P
SYNC
= (1 – DC)(I
MAX
)
2
(1 + δ)(R
DS(ON)
)
The (1 + δ) term in the above relations is the temperature
dependency of R
DS(ON)
, typically given in the form of a
normalized R
DS(ON)
vs Temperature curve in a MOSFET
data sheet.
In some applications, parasitic FET capacitances couple
the negative going switch node transient onto the bottom
gate drive pin of the LT1339, causing a negative voltage in
excess of the Absolute Maximum Rating to be imposed on
that pin. Connection of a catch Schottky (rated to about 1A
is typically sufficient) from this pin to ground will eliminate
this effect.
C
IN
and C
OUT
Supply Decoupling Capacitor Selection
The large currents typical of LT1339 applications require
special consideration for the converter input and output
supply decoupling capacitors. Under normal steady state
operation, the source current of the main switch MOSFET
is a square wave of duty cycle V
OUT
/V
IN
. Most of this
current is provided by the input bypass capacitor. To
prevent large input voltage transients and avoid bypass
capacitor heating, a low ESR input capacitor sized for the
maximum RMS current must be used. This maximum
capacitor RMS current follows the relation:
I
IVVV
V
RMS
MAX OUT IN OUT
IN
() ( )
()
/12
which peaks at a 50% duty cycle, when I
RMS
= I
MAX
/2.
Capacitor ripple current ratings are often based on only

LT1339CSW#PBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators High Pwr Synch DC/DC Controller
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