LT1339ISW#PBF Datasheet LT1339IN#PBF, LT1339CSW#TRPBF, LT1339ISW#TRPBF | P7-P9

LT1339

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SYNC (Pin 1): Oscillator Synchronization Pin with TTL-

Level Compatible Input. Input drives internal rising edge

triggered one-shot; sync signal on/off times should be

≥1µs (10% to 90% DC at 100kHz). Does not contain

internal pull-up. Connect to SGND if not used.

REF

(Pin 2): 5V Output Reference. Allows connection

of external loads up to 10mA DC. (Reference is not

available in shutdown.) Typically bypassed with 1µF

capacitor to SGND.

CT (Pin 3): Oscillator Timing Pin. Connect a capacitor

) to ground and a pull-up resistor (R

) to the 5V

REF

supply. Typical values are CT = 1000pF and 10k ≤ R

≤ 30k.

SL/ADJ (Pin 4): Slope Compensation Adjustment.

Allows increased slope compensation for certain high

duty cycle applications. Resistive loading of the pin

increases effective slope compensation. A resistor

divider from the 5V

REF

pin can tailor the onset of addi-

tional slope compensation to specific regions in each

switch cycle. Pin can be floated or connected to 5V

REF

no additional slope compensation is required. (See

Applications Information section for slope compensa-

tion details.)

AVG

(Pin 5): Average Current Limit Integration. Fre-

quency response characteristic is set using the 50kΩ

output impedance and external capacitor to ground.

Averaging roll-off typically set at 1 to 2 orders of magni-

tude under switching frequency. (Typical capacitor value

~1000pF for f

= 100kHz.) Shorting this pin to SGND will

disable the average current limit function.

SS (Pin 6): Soft Start. Generates ramping threshold for

regulator current limit during start-up and after UVLO

event by sourcing about 8µA into an external capacitor.

(Pin 7): Error Amplifier Output. RC load creates

dominant compensation in power supply regulation feed-

back loop to provide optimum transient response. (See

Applications Information section for compensation de-

tails.)

SGND (Pin 8): Small-Signal Ground. Connect to negative

terminal of C

OUT

(Pin 9): Error Amplifier Inverting Input. Used as

voltage feedback input node for regulator loop. Pin

sources about 0.5µA DC bias current to protect from an

open feedback path condition.

PIN FUNCTIONS

UUU

REF

(Pin 10): Bandgap Generated Voltage Reference

Decoupling. Connect a capacitor to signal ground. (Typi-

cal capacitor value ~0.1µF.)

SENSE

(Pin 11): Current Sense Amplifier Inverting

Input. Connect to most positive (DC) terminal of current

sense resistor.

SENSE

–

(Pin 12): Current Sense Amplifier Noninverting

Input. Connect to most negative (DC) terminal of current

sense resistor.

RUN/SHDN (Pin 13): Precision Referenced Shutdown.

Can be used as logic level input for shutdown control or

as an analog monitor for input supply undervoltage

protection, etc. IC is enabled when RUN/SHDN pin rising

edge exceeds 1.25V. About 25mV of hysteresis helps

assure stable mode switching. All internal functions are

disabled in shutdown mode. If this function is not

desired, connect RUN/SHDN to 12V

(typically through

a 100k resistor). See Applications Information section.

PHASE (Pin 14): Output Driver Phase Control. If Pin 14

is not connected (floating), the topside driver operates

the main switch, with the bottom side driver operating

the synchronous switch. Shorting Pin 14 to ground

reverses the roles of the output drivers. PHASE is typi-

cally shorted to ground for inverting and boost configu-

rations. Positive buck configuration requires the PHASE

pin to float. See Applications Information section.

PGND (Pin 15): Power Ground. References the bottom

side output switch and internal driver control circuits.

Connect with low impedance trace to V

decoupling

capacitor negative (ground) terminal.

BG (Pin 16): Bottom Side Output Driver. Connects to gate

of bottom side external power FET.

12V

(Pin 17): 12V Power Supply Input. Bypass with at

least 1µF to PGND.

TS (Pin 18): Boost Output Driver Reference. Typically

connects to source of topside external power FET and

inductive switch node.

TG (Pin 19): Topside (Boost) Output Driver. Connects to

gate of topside external power FET.

BOOST

(Pin 20): Topside Power Supply. Bootstrapped

via 1µF capacitor tied to switch node (Pin 18) and

Schottky diode connected to the 12V

supply.

LT1339

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OPERATION

Basic Control Loop

The LT1339 uses a constant frequency, current mode

synchronous architecture. The timing of the IC is provided

through an internal oscillator circuit, which can be syn-

chronized to an external clock, programmable to operate

at frequencies up to 150kHz. The oscillator creates a

modified sawtooth wave at its timing node (CT) with a slow

charge, rapid discharge characteristic.

During typical positive buck operation, the main switch

MOSFET is enabled at the start of each oscillator cycle. The

main switch stays enabled until the current through the

switched inductor, sensed via the voltage across a series

(Refer to Functional Block Diagram)

sense resistor (R

SENSE

), is sufficient to trip the current

comparator (IC1) and, in turn, reset the RS latch. When the

RS latch resets, the main switch is disabled, and the

synchronous switch MOSFET is enabled. Shoot-through

prevention logic prohibits enabling of the synchronous

switch until the main switch is fully disabled. If the current

comparator threshold is not obtained throughout the

entire oscillator charge period, the RS latch is bypassed

and the main switch is disabled during the oscillator

discharge time. This “minimum off time” assures ad-

equate charging of the bootstrap supply, protects the main

switch, and is typically about 1µs.

–

1.25V

SOFT START

8µA

AVG

–

1.25V

REFERENCE

0.5µA

× 15

CURRENT

SENSE AMP

IC1

OSC

SL/ADJ

NONOVERLAPPING

SWITCH LOGIC

UVLO

CIRCUIT

BOOST

PHASE

12V

SENSE

REF

MAIN

SWITCH

SYNC

SWITCH

SENSE

–

SENSE

OUT

1339 • BD

CIRCUIT

ENABLE

–

2.5V

PGNDSGND

ONE SHOT

50k

AVERAGE

CURRENT

LIMIT

RUN/SHDN

REF

SYNC

FU CTIO AL BLOCK DIAGRA

LT1339

sn1339 1339fas

OPERATION

(Refer to Functional Block Diagram)

The current comparator trip threshold is set on the V

pin,

which is the output of a transconductance amplifier, or

error amplifier (EA). The error amplifier integrates the

difference between a feedback voltage (on the V

pin)

and an internal bandgap generated reference voltage of

1.25V, forming a signal that represents required load

current. If the supplied current is insufficient for a given

load, the output will droop, thus reducing the feedback

voltage. The error amplifier forces current out of the V

pin, increasing the current comparator threshold. Thus,

the circuit will servo until the provided current is equal to

the required load and the average output voltage is at the

value programmed by the feedback resistors.

Average Current Limit

The output of the sense amplifier is monitored by a single

pole integrator comprised of an external capacitor on the

AVG

pin and an internal impedance of approximately

50kΩ. If this averaged value signal exceeds a level corre-

sponding to 120mV across the external sense resistor, the

current comparator threshold is clamped and cannot

continue to rise in response to the error amplifier. Thus, if

average load current requirements exceed 120mV/R

SENSE

the supply will current limit and the output voltage will fall

out of regulation. The average current limit circuit moni-

tors the sense amplifier output without slope compensa-

tion or ripple current contributions, therefore the average

load current limit threshold is unaffected by duty cycle.

Undervoltage Lockout

The LT1339 employs an undervoltage lockout circuit

(UVLO) that monitors the 12V supply rail. This circuit

disables the output drive capability of the LT1339 if

the 12V supply drops below about 9V. Unstable mode

switching is prevented through 350mV of UVLO threshold

hysteresis.

Adaptive Nonoverlapping Output Stage

The FET driver output stage implements adaptive

nonoverlapping control. This circuitry maintains dead

time independent of the type, size or operating conditions

of the switch elements. The control circuit monitors the

output gate drive signals, insuring that the switch gate

(being disabled) is fully discharged before enabling the

other switch driver.

Shutdown

The LT1339 can be put into low current shutdown mode

by pulling the RUN/SHDN pin low, disabling all circuit

functions. The shutdown threshold is a bandgap referred

voltage of 1.25V typical. Use of a precision threshold on

the shutdown circuit enables use of this pin for undervolt-

age protection of the V

supply and/or power supply

sequencing.

Soft Start

The LT1339 incorporates a soft start function that oper-

ates by slowly increasing the internal current limit. This

limit is controlled by clamping the V

node to a low voltage

that climbs with time as an external capacitor on the SS pin

is charged with about 8µA. This forces a graceful climb of

output current capability, and thus a graceful increase in

output voltage until steady-state regulation is achieved.

The soft start timing capacitor is clamped to ground

during shutdown and during undervoltage lockout, yield-

ing a graceful output recovery from either condition.

5V Internal Reference

Power for the oscillator timing elements and most other

internal LT1339 circuits is derived from an internal 5V

reference, accessible at the 5V

REF

pin. This supply pin can be

loaded with up to 10mA DC (20mA pulsed) for convenient

biasing of local elements such as control logic, etc.

Slope Compensation

For duty cycles greater than 50%, slope compensation is

required to prevent current mode duty cycle instability in

the regulator control loop. The LT1339 employs internal

slope compensation that is adequate for most applica-

tions. However, if additional slope compensation is

desired, it is available through the SL/ADJ pin. Excessive

slope compensation will cause reduction in maximum

load current capability and therefore is not desirable.

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LT1339ISW#PBF

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Switching Voltage Regulators High Pwr Synch DC/DC Controller

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LT1339ISW#PBF

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