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LTC1864HMS8#PBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24
LTC1864/LTC1865
13
18645fb
LTC1864 OPERATION
Operating Sequence
The LTC1864 conversion cycle begins with the rising edge
of CONV. After a period equal to t
CONV
, the conversion is
fi nished. If CONV is left high after this time, the LTC1864
goes into sleep mode drawing only leakage current. On the
falling edge of CONV, the LTC1864 goes into sample mode
and SDO is enabled. SCK synchronizes the data transfer
with each bit being transmitted from SDO on the falling
SCK edge. The receiving system should capture the data
from SDO on the rising edge of SCK. After completing the
data transfer, if further SCK clocks are applied with CONV
low, SDO will output zeros indefi nitely. See Figure 1.
Analog Inputs
The LTC1864 has a unipolar differential analog input. The
converter will measure the voltage between the “IN
+
”
and “IN
–
” inputs. A zero code will occur when IN
+
minus
IN
–
equals zero. Full scale occurs when IN
+
minus IN
–
equals V
REF
minus 1LSB. See Figure 2. Both the “IN
+
” and
“IN
–
” inputs are sampled at the same time, so common
mode noise on the inputs is rejected by the ADC. If “IN
–
”
is grounded and V
REF
is tied to V
CC
, a rail-to-rail input
span will result on “IN
+
” as shown in Figure 3.
Reference Input
The voltage on the reference input of the LTC1864 defi nes
the full-scale range of the A/D converter. The LTC1864 can
operate with reference voltages from V
CC
to 1V.
APPLICATIONS INFORMATION
Figure 1. LTC1864 Operating Sequence
Figure 2. LTC1864 Transfer Curve Figure 3. LTC1864 with Rail-to-Rail Input Span
CONV
t
CONV
SCK
SDO
16151413121110987654321
B15
B14 B12 B10 B8 B6 B4 B2 B0*
Hi-Z
18645 F01
Hi-Z
B13
B11 B9 B7 B5 B3 B1
SLEEP MODE
t
SMPL
*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER SCK CLOCKS ARE
APPLIED WITH CONV LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY
t
suCONV
0V
1LSB
V
REF
– 2LSB
V
REF
– 1LSB
V
REF
V
IN
*
*V
IN
= IN
+
– IN
–
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
•
•
•
18645 F02
1
2
3
4
8
7
6
5
V
REF
IN
+
IN
–
GND
V
CC
SCK
SDO
CONV
LTC1864
18645 F03
V
IN
= 0V TO V
CC
V
CC
1μF
SERIAL DATA LINK TO
ASIC, PLD, MPU, DSP
OR SHIFT REGISTERS
LTC1864/LTC1865
14
18645fb
APPLICATIONS INFORMATION
LTC1865 OPERATION
Operating Sequence
The LTC1865 conversion cycle begins with the rising edge
of CONV. After a period equal to t
CONV
, the conversion is
fi nished. If CONV is left high after this time, the LTC1865
goes into sleep mode drawing only leakage current. The
LTC1865’s 2-bit data word is clocked into the SDI input
on the rising edge of SCK after CONV goes low. Additional
inputs on the SDI pin are then ignored until the next CONV
cycle. The shift clock (SCK) synchronizes the data transfer
with each bit being transmitted on the falling SCK edge and
captured on the rising SCK edge in both transmitting and
receiving systems. The data is transmitted and received
simultaneously (full duplex). After completing the data
transfer, if further SCK clocks are applied with CONV low,
SDO will output zeros indefi nitely. See Figure 4.
Analog Inputs
The two bits of the input word (SDI) assign the MUX
confi guration for the next requested conversion. For a
given channel selection, the converter will measure the
voltage between the two channels indicated by the “+”
and “–” signs in the selected row of the following table. In
single-ended mode, all input channels are measured
with respect to GND. A zero code will occur when the
“+” input minus the “–” input equals zero. Full scale oc-
curs when the “+” input minus the “–” input equals V
REF
minus 1LSB. See Figure 5. Both the “+” and “–” inputs
are sampled at the same time so common mode noise
is rejected. The input span in the SO-8 package is fi xed
at V
REF
= V
CC
. If the “–” input in differential mode is
grounded, a rail-to-rail input span will result on the “+”
input.
Reference Input
The reference input of the LTC1865 SO-8 package is
internally tied to V
CC
. The span of the A/D converter is
therefore equal to V
CC
. The voltage on the reference
input of the LTC1865 MSOP package defi nes the span
of the A/D converter. The LTC1865 MSOP package can
operate with reference voltages from 1V to V
CC
.
Figure 4. LTC1865 Operating Sequence
MUX ADDRESS
Table 1. Multiplexer Channel Selection
SGL/DIFF
1
1
0
0
ODD/SIGN
0
1
0
1
CHANNEL #
0
+
+
–
1
+
–
+
GND
–
–
18645 TBL1
SINGLE-ENDED
MUX MODE
DIFFERENTIAL
MUX MODE
CONV
SDI
SCK
16151413121110987654321
SDO
B15
B14 B12 B10 B8 B6 B4 B2
B0*
Hi-Z
B13
B11 B9 B7 B5 B3 B1
S/D O/S
DON’T CAREDON’T CARE
t
CONV
18645 F04
SLEEP MODE
*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER SCK CLOCKS ARE
APPLIED WITH CONV LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY
Hi-Z
t
SMPL
LTC1864/LTC1865
15
18645fb
APPLICATIONS INFORMATION
GENERAL ANALOG CONSIDERATIONS
Grounding
The LTC1864/LTC1865 should be used with an analog
ground plane and single point grounding techniques. Do not
use wire wrapping techniques to breadboard and evaluate
the device. To achieve the optimum performance, use a
printed circuit board. The ground pins (AGND and DGND
for the LTC1865 MSOP package and GND for the LTC1864
and LTC1865 SO-8 package) should be tied directly to the
analog ground plane with minimum lead length.
Bypassing
For good performance, the V
CC
and V
REF
pins must be free
of noise and ripple. Any changes in the V
CC
/V
REF
voltage
with respect to ground during the conversion cycle can
induce errors or noise in the output code. Bypass the V
CC
and V
REF
pins directly to the analog ground plane with
a minimum of 1μF tantalum. Keep the bypass capacitor
leads as short as possible.
Analog Inputs
Because of the capacitive redistribution A/D conversion
techniques used, the analog inputs of the LTC1864/LTC1865
have capacitive switching input current spikes. These cur-
rent spikes settle quickly and do not cause a problem if
source resistances are less than 200Ω or high speed op
amps are used (e.g., the LT
®
1211, LT1469, LT1807, LT1810,
LT1630, LT1226 or LT1215). But if large source resistances
are used, or if slow settling op amps drive the inputs, take
care to ensure the transients caused by the current spikes
settle completely before the conversion begins.
Figure 5. LTC1865 Transfer Curve
0V
1LSB
V
CC
– 2LSB
V
CC
– 1LSB
V
CC
V
IN
*
*V
IN
= (SELECTED “+” CHANNEL) –
(SELECTED “–” CHANNEL)
REFER TO TABLE 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
•
•
•
18645 F05
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24

LTC1864HMS8#PBF

Mfr. #:
Buy LTC1864HMS8#PBF
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 16-bit, 250ksps ADC in MSOP
Lifecycle:
New from this manufacturer.
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