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AT17C002-10CC

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19
1
Features
• EE Reprogrammable 2,097,152 x 1-bit Serial Memories Designed to Store
Configuration Programs for Field Programmable Gate Arrays (FPGAs)
• In-System Programmable via 2-wire Bus
• Simple Interface to SRAM FPGAs
• Compatible with Atmel AT6000, AT40K and AT94K Devices, Altera FLEX
®
, APEX
™
Devices, Lucent ORCA
®
FPGAs, Xilinx XC3000
™
, XC4000
™
, XC5200
™
, Spartan
®
,
Virtex
™
FPGAs
• Cascadable Read Back to Support Additional Configurators or Higher-density Arrays
• Low-power CMOS EEPROM Process
• Programmable Reset Polarity
• Available in 6 mm x 6 mm x 1 mm 8-lead LAP (Pin-compatible with 8-lead SOIC/VOIC
Packages), 20-lead PLCC, 44-lead PLCC and 44-lead TQFP Packages (Pin-compatible
Across Product Family)
• Emulation of Atmel’s AT24CXXX Serial EEPROMs
• Available in 3.3V ± 10% LV and 5V ± 5% C Versions
• System-friendly READY Pin
• Low-power Standby Mode
• Replacement for AT17C/LV020
Description
The AT17C002 and AT17LV002 (high-density AT17 Series) FPGA Configuration
EEPROMs (Configurators) provide an easy-to-use, cost-effective configuration mem-
ory for programming Field Programmable Gate Arrays. The AT17 Series is packaged
in the popular 8-lead LAP, 20-lead PLCC, 44-lead PLCC and the 44-lead TQFP. The
AT17 Series family uses a simple serial-access procedure to configure one or more
FPGA devices. The user can select the polarity of the reset function by programming
four EEPROM bytes. These devices support a write protection mode and a system-
friendly READY pin, which signifies a “good” power level to the FPGA and can be used
to ensure reliable system power-up.
The AT17 Series Configurators can be programmed with industry-standard program-
mers, Atmel’s ATDH2200E Programming System and Atmel’s ATDH2225 ISP Cable.
FPGA
Configuration
EEPROM
Memory
2-megabit
AT17C002
AT17LV002
Rev. 2281D–12/01
2
AT17C/LV002
2281D–12/01
Pin Configuration
8-lead LAP
44-lead PLCC
8
7
6
5
1
2
3
4
DATA
CLK
RESET/OE
CE
VCC
SER_EN
CEO (A2)
GND
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
6
5
4
3
2
1
44
43
42
41
40
18
19
20
21
22
23
24
25
26
27
28
NC
RESET/OE
NC
CE
NC
NC
GND
NC
NC
CEO(A2)
NC
NC
CLK
NC
NC
DATA
NC
VCC
NC
NC
SER_EN
NC
WP1
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
READY
20-lead PLCC
44-lead TQFP
4
5
6
7
8
18
17
16
15
14
CLK
WP1
RESET/OE
NC
CE
NC
SER_EN
NC
READY
CEO(A2)
3
2
1
20
19
9
10
11
12
13
NC
GND
NC
NC
NC
NC
DATA
NC
VCC
NC
1
2
3
4
5
6
7
8
9
10
11
33
32
31
30
29
28
27
26
25
24
23
44
43
42
41
40
39
38
37
36
35
34
12
13
14
15
16
17
18
19
20
21
22
NC
RESET/OE
NC
CE
NC
NC
GND
NC
NC
CEO(A2)
NC
NC
CLK
NC
NC
DATA
NC
VCC
NC
NC
SER_EN
NC
NC
NC
NC
NC
NC
NC
WP1
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
READY
3
AT17C/LV002
2281D–12/01
Block Diagram
Device Description
The control signals for the configuration EEPROM (CE, RESET/OE and CCLK) inter-
face directly with the FPGA device control signals. All FPGA devices can control the
entire configuration process and retrieve data from the configuration EEPROM without
requiring an external intelligent controller.
The configuration EEPROM RESET/OE
and CE pins control the tri-state buffer on the
DATA output pin and enable the address counter. When RESET/OE
is driven High, the
configuration EEPROM resets its address counter and tri-states its DATA pin. The CE
pin also controls the output of the AT17 Series Configurator. If CE is held High after the
RESET/OE
reset pulse, the counter is disabled and the DATA output pin is tri-stated.
When OE
is subsequently driven Low, the counter and the DATA output pin are
enabled. When RESET/OE
is driven High again, the address counter is reset and the
DATA output pin is tri-stated, regardless of the state of CE
.
When the configurator has driven out all of its data and CEO
is driven Low, the device
tri-states the DATA pin to avoid contention with other configurators. Upon power-up, the
address counter is automatically reset.
This is the default setting for the device. Since almost all FPGAs use RESET Low and
OE High, this document will describe RESET
/OE.
EEPROM
CELL
MATRIX
ROW
DECODER
COLUMN
DECODER
TC
CECLK
READY RESET/OE CEO(A2) DATA
BIT
COUNTER
OSC
OSC
CONTROL
PROGRAMMING
DATA SHIFT
REGISTER
PROGRAMMING
MODE LOGIC
ROW
ADDRESS
COUNTER
POWER ON
RESET
SER_EN
WP1
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19

AT17C002-10CC

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Description:
IC SRL CONFIG EEPROM 2M 8LAP
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