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Document Number: 63717
S13-0971-Rev. F, 06-May-13
Vishay Siliconix
SiP32408, SiP32409
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
For technical questions, contact: powerictechsupport@vishay.com
It then follows that, assuming an ambient temperature of
70 °C, the maximum power dissipation will be limited to about
324 mW.
So long as the load current is below the 3.5 A limit, the
maximum continuous switch current becomes a function of
two things: the package power dissipation and the R
DS(on)
at
the ambient temperature.
As an example let us calculate the worst case maximum load
current at T
A
= 70 °C. The worst case R
DS(on)
at 25 °C occurs
at an input voltage of 1.2 V and is equal to 52 m. The
R
DS(on)
at 70 °C can be extrapolated from this data using the
following formula:
R
DS(on)
(at 70 °C) = R
DS(on)
(at 25 °C) x (1 + T
C
x DT)
Where T
C
is 3300 ppm/°C. Continuing with the calculation
we have
R
DS(on)
(at 70 °C) = 52 m x (1 + 0.0033 x (70 °C - 25 °C))
= 60 m
The maximum current limit is then determined by
which in this case is 2.3 A. Under the stated input voltage
condition, if the 2.3 A current limit is exceeded the internal die
temperature will rise and eventually, possibly damage the
device.
Active EN Pull Down for Reverse Blocking
When an internal circuit detects the condition of V
OUT
0.8 V
higher than V
IN
, it will turn on the pull down circuit connected
to EN, forcing the switching OFF. The pull down value is
about 1 k.
Pulse Current Capability
The device is mounted on the evaluation board shown in the
PCB layout section. It is loaded with pulses of 5 A and 1 ms
for periods of 4.6 ms.
SiP32408 and SiP32409 can safely support 5 A pulse
current repetitively at 25 °C.
Switch Non-Repetitive Pulsed Current
SiP32408 and SiP32409 can withstand inrush current of up
to 12 A for 100 µs at 25 °C when heavy capacitive loads are
connected and the part is already enabled.
Recommended Board Layout
For the best performance, all traces should be as short as
possible to minimize the inductance and parasitic effects.
The input and output capacitors should be kept as close
as possible to the input and output pins respectively.
Connecting the central exposed pad to GND, using wide
traces for input, output, and GND help reducing the case to
ambient thermal impedance.
) (
(max.)
(max.)
ON DS
LOAD
R
P
I <
IN
EN
OUT
Reverse
Blocking
Charge
Pump
Control Logic
Input Buffer
Pull Down
Circuit
Control and Drive
V
OUT
> V
IN
Detect
When V
OUT
is 0.8 V above the V
IN
, pull down circuit
will be activated. It connects the EN to GND with a
resistance of around 1 kΩ.
