DS_8010R_022 73S8010R Data Sheet
Rev. 1.6 19
3.7 Activation Sequence
After Power on Reset, the signal INT is low until the V
DD
is stable. When V
DD
has been stable for
approximately 10 ms and the signal INT is high, the system controller may read the status register to see
if the card is present. If all the status bits are satisfied, the system controller can initiate the activation
sequence by writing a '1' to the Start/Stop bit (bit 0) of the control register.
The following steps and Figure 8 show the activation sequence and the timing of the card control signals
when the system controller initiates the Start/Stop bit (bit 0) of the control register:
1. Voltage V
CC
to the card should be valid by the end of t
1
. If V
CC
is not valid for any reason, then
the session is aborted.
2. Turn I/O to reception mode at the end of t
1
.
3. CLK is applied to the card at the end of t
2
.
4. RST (to the card) is set high at the end of t
3
.
Start/Stop
VCC
IO
CLK
RST
t
1
t
2
t
3
t
1
= 0.510 ms (timing by 1.5MHz internal Oscillator), I/O in reception mode
t
2
=1.5 μs, CLK starts
t
3
= >42000 card clock cycles, RST set high
Figure 8: Activation Sequence
3.8 Deactivation Sequence
Deactivation is initiated either by the system controller by resetting the Start/Stop bit, or automatically in
the event of hardware faults. Hardware faults are over-current, over-temperature, V
DD
fault, V
PC
fault, V
CC
fault, and card extraction during the session.
The following steps and Figure 9 show the deactivation sequence and the timing of the card control
signals when the system controller clears the start/stop bit:
1. RST goes low at the end of t
1
.
2. CLK goes low at the end of t
2
.
3. I/O goes low at the end of t
3
. Out of reception mode.
4. Shut down V
CC
at the end of time t
4
.
