OP275
–8–
OP275
–9–
+15V
+
0.1
F
2
3
8
1
4
V
IN
V
OUT
R
L
2k
–15V
10F
0.1
F
1/2
OP275
10F
+
+
Figure 12. Unity Gain Follower
0.1
F
+15V
+
10
F
2
3
8
1
4
V
IN
V
OUT
2k
–15V
10
F
0.1
F
10pF
4.99k
2.49k
4.99k
+
1/2
OP275
+
Figure 13. Unity Gain Inverter
In inverting and noninverting applications, the feedback resis-
tance forms a pole with the source resistance and capacitance
(R
S
and C
S
) and the OP275’s input capacitance (C
IN
), as shown
in Figure 14. With R
S
and R
F
in the kilohm range, this pole
can create excess phase shift and even oscillation. A small
capacitor, C
FB
, in parallel and R
FB
eliminates this problem.
By setting R
S
(C
S
+ C
IN
) = R
FB
C
FB
, the effect of the feedback
pole is completely removed.
16V–20V
0.1F
V+
5V
R
L
1k
D1 D2
+15V
2N4416
1k
D3
D4
OUTPUT
(TO SCOPE)
1F
10k
IC
2
R
F
2k
750
2N2222A
15k
–15V
1N4148
DUT
1/2 OP260AJ
16V–20V
0.1F
10k
+
+
SCHOTTKY DIODES D1–D4 AR
E
HEWLETT-PACKARD HP5082-2835
IC1 IS 1/2 OP260AJ
IC2 IS PMI OP41EJ
V–
R
G
222
+
+
+
Figure 11. OP275’s Settling Time Test Fixture
R
FB
C
IN
R
S
C
S
C
FB
V
OUT
+
Figure 14. Compensating the Feedback Pole
Attention to Source Impedances Minimizes Distortion
Since the OP275 is a very low distortion amplier, careful atten-
tion should be given to source impedances seen by both inputs.
As with many FET-type ampliers, the p-channel JFETs in the
OP275’s input stage exhibit a gate-to-source capacitance that var-
ies with the applied input voltage. In an inverting conguration,
the inverting input is held at a virtual ground and, as such, does
not vary with input voltage. Thus, since the gate-to-source voltage
is constant, there is no distortion due to input capacitance modu-
lation. In noninverting applications, however, the gate-to-source
voltage is not constant. The resulting capacitance modulation
can cause distortion above 1 kHz if the input impedance is
greater than 2 k
and unbalanced.
OP275
V
IN
V
OUT
R
F
R
G
R
S*
*
R
S
= R
G
//R
F
IF R
G
//R
F
> 2k
FOR MINIMUM DISTORTION
+
Figure 15. Balanced Input Impedance to Minimize
Distortion in Noninverting Amplier Circuits
Figure 15 shows some guidelines for maximizing the distortion
performance of the OP275 in noninverting applications. The best
way to prevent unwanted distortion is to ensure that the parallel
combination of the feedback and gain setting resistors (R
F
and
R
G
) is less than 2 k
. Keeping the values of these resistors small
has the added benets of reducing the thermal noise of the circuit
REV. C
REV. C
OP275
–10–
OP275
–11–
and dc offset errors. If the parallel combination of R
F
and R
G
is
larger than 2 k
, then an additional resistor, R
S
, should be used
in series with the noninverting input. The value of R
S
is deter-
mined by the parallel combination of R
F
and R
G
to maintain the
low distortion performance of the OP275.
Driving Capacitive Loads
The OP275 was designed to drive both resistive loads to 600
and capacitive loads of over 1000 pF and maintain stability. While
there is a degradation in bandwidth when driving capacitive loads,
the designer need not worry about device stability. The graph in
Figure 16 shows the 0 dB bandwidth of the OP275 with capaci-
tive loads from 10 pF to 1000 pF.
10
9
8
7
6
5
4
3
2
1
0
0 200 400 600 800 1000
C
LOAD
– pF
BANDWIDTH – MHz
Figure 16. Bandwidth vs. C
LOAD
High Speed, Low Noise Differential Line Driver
The circuit in Figure 17 is a unique line driver widely used in
industrial applications. With ±18 V supplies, the line driver can
deliver a differential signal of 30 V p-p into a 2.5 k
load. The
high slew rate and wide bandwidth of the OP275 combine to
yield a full power bandwidth of 130 kHz while the low noise
front end produces a referred-to-input noise voltage spectral
density of 10 nV/
Hz.
1
2
3
A2
1
3
2
A1
5
6
7
A3
V
IN
V
O1
V
O2
R3
2k
R9
50
R11
1k
P1
10k
R12
1k
R10
50
R8
2k
R2
2k
R5
2k
R4
2k
R1
2k
R7
2k
V
O2
– V
O1
= V
IN
A1 = 1/2 OP275
A2, A3 = 1/2 OP275
GAIN =
SET R2, R4, R5 = R1 AND R6, R7, R8 = R3
R3
R1
R6
2k
+
+
+
Figure 17. High Speed, Low Noise Differential Line Driver
The design is a transformerless, balanced transmission system
where output common-mode rejection of noise is of paramount
importance. Like the transformer based design, either output can
be shorted to ground for unbalanced line driver applications
without changing the circuit gain of 1. Other circuit gains can be
set according to the equation in the diagram. This allows the
design to be easily set to noninverting, inverting, or differential
operation.
A 3-Pole, 40 kHz Low-Pass Filter
The closely matched and uniform ac characteristics of the OP275
make it ideal for use in GIC (Generalized Impedance Converter)
and FDNR (Frequency-Dependent Negative Resistor) lter
applications. The circuit in Figure 18 illustrates a linear-phase,
3-pole, 40 kHz low-pass lter using an OP275 as an inductance
simulator (gyrator). The circuit uses one OP275 (A2 and A3) for
the FDNR and one OP275 (A1 and A4) as an input buffer and
bias current source for A3. Amplier A4 is congured in a gain
of 2 to set the pass band magnitude response to 0 dB. The ben-
ets of this lter topology over classical approaches are that the
op amp used in the FDNR is not in the signal path and that the
lter’s performance is relatively insensitive to component varia-
tions. Also, the conguration is such that large signal levels can
be handled without overloading any of the lter’s internal nodes.
As shown in Figure 19, the OP275’s symmetric slew rate and low
distortion produce a clean, well behaved transient response.
V
IN
3
2
1
A1
R1
95.3k
R2
787
C1
2200pF
C2
2200pF
R3
1.82k
C3
2200pF
R4
1.87k
R5
1.82k
A2
1
2
3
5
6
7
A3
R6
4.12k
C4
2200pF
R7
100k
5
6
7
A4
R8
1k
R9
1k
V
OUT
A1, A4 = 1/2 OP275
A2, A3 = 1/2 OP275
+
+
+
+
Figure 18. A 3-Pole, 40 kHz Low-Pass Filter
V
OUT
10V p-p
10kHz
SCALE: VERTICAL–2V/ DIV
HORIZONTAL–10
s/ DIV
10
0%
100
90
Figure 19. Low-Pass Filter Transient Response
REV. C
REV. C
OP275
–10–
OP275
–11–
OP275 SPICE Model
*
* Node assignments
* noninverting input
* inverting input
* positive supply
* negative supply
* output
**
.SUBCKT OP275 1 2 99 50 34
*
* INPUT STAGE & POLE AT 100 MHz
*
R3 5 51 2.188
R4 6 51 2.188
CIN 1 2 3.7E-12
CM1 1 98 7.5E-12
CM2 2 98 7.5E-12
C2 5 6 364E-12
I1 97 4 100E-3
IOS 1 2 1E-9
EOS 9 3 POLY(1) 26 28 0.5E-3 1
Q1 5 2 7 QX
Q2 6 9 8 QX
R5 7 4 1.672
R6 8 4 1.672
D1 2 36 DZ
D2 1 36 DZ
EN 3 1 10 0 1
GN1 0 2 13 0 1E-3
GN2 0 1 16 0 1E-3
*
EREF 98 0 28 0 1
EP 97 0 99 0 1
EM 51 0 50 0 1
*
* VOLTAGE NOISE SOURCE
*
DN1 35 10 DEN
DN2 10 11 DEN
VN1 35 0 DC 2
VN2 0 11 DC 2
*
* CURRENT NOISE SOURCE
*
DN3 12 13 DIN
DN4 13 14 DIN
VN3 12 0 DC 2
VN4 0 14 DC 2
*
* CURRENT NOISE SOURCE
*
DN5 15 16 DIN
DN6 16 17 DIN
VN5 15 0 DC 2
VN6 0 17 DC 2
*
* GAIN STAGE & DOMINANT POLE AT 32 Hz
*
R7 18 98 1.09E6
C3 18 98 4.55E-9
G1 98 18 5 6 4.57E-1
V2 97 19 1.35
V3 20 51 1.35
D3 18 19 DX
D4 20 18 DX
* POLE/ZERO PAIR AT 1.5 MHz/2.7 MHz
*
R8 21 98 1E-3
R9 21 22 1.25E-3
C4 22 98 47.2E-12
G2 98 21 18 28 1E-3
*
* POLE AT 100 MHz
*
R10 23 98 1
C5 23 98 1.59E-9
G3 98 23 21 28 1
*
* POLE AT 100 MHz
*
R11 24 98 1
C6 24 98 1.59E-9
G4 98 24 23 28 1
*
* COMMON-MODE GAIN NETWORK WITH ZERO AT
1 kHz
*
R12 25 26 1E6
C7 25 26 1.5915E-12
R13 26 98 1
E2 25 98 POLY(2) 1 98 2 98 0 2.50
2.50
*
* POLE AT 100 MHz
*
R14 27 98 1
C8 27 98 1.59E-9
G5 98 27 24 28 1
*
* OUTPUT STAGE
*
R15 28 99 100E3
R16 28 50 100E3
C9 28 50 1E-6
ISY 99 50 1.85E-3
R17 29 99 100
R18 29 50 100
L2 29 34 1E-9
G6 32 50 27 29 10E-3
G7 33 50 29 27 10E-3
G8 29 99 99 27 10E-3
G9 50 29 27 50 10E-3
V4 30 29 1.3
V5 29 31 3.8
F1 29 0 V4 1
F2 0 29 V5 1
D5 27 30 DX
D6 31 27 DX
D7 99 32 DX
D8 99 33 DX
D9 50 32 DY
D10 50 33 DY
*
* MODELS USED
*
.MODEL QX PNP(BF=5E5)
.MODEL DX D(IS=1E-12)
.MODEL DY D(IS=1E-15 BV=50)
.MODEL DZ D(IS=1E-15 BV=7.0)
.MODEL DEN D(IS=1E-12 RS=4.35K KF=1.95E-15
AF=1)
.MODEL DIN D(IS=1E-12 RS=268 KF=1.08E-15 AF=1)
.ENDS
REV. C
REV. C

OP275GSZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Audio Amplifiers Bipolar/JFET Audio Dual 1mV 2nA
Lifecycle:
New from this manufacturer.
Delivery:
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