(V
DD
= +10V to +40V, VL = +2.5V to +5.5V, R
LIM
= 27kΩ to 220kΩ, T
A
= -40°C to +125°C, unless otherwise noted. Typical values are
at T
A
= +25°C and V
DD
= +24V, VL = +3.3V and V5 = +5V, R
LIM
= 50kΩ) (Note 2)
Note 2: All units are production tested at T
A
= +25°C. Specification over temperature are guaranteed by characterization and design.
Note 3: Specification is guaranteed by design; not production tested.
Note 4: Lower resistor values than CLIM_SHORT act like a CLIM pin short to GND.
Note 5: Higher resistor values than CLIM_OPEN act like a CLIM open circuit.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
TIMING CHARACTERISTICS
OUTPUT DRIVER (DOI)
Output Propagation Delay
LH
t
PD_LH
PP = X, delay from IN to DOI rising by 1V,
R
L
= 5kΩ, C
L
= 100pF (Figure 1)
0.4 1.5 µs
Output Propagation Delay
HL
t
PD_HL
PP = low, delay between IN switching low
to DOI falling by 1V. R
L
= 5kΩ,
C
L
= 100pF, V
DD
= 24V (Figure 1)
0.6 1.5
µs
PP = high, delay between IN switching
low to DOI falling by 1V. R
L
= 5kΩ,
C
L
= 100pF (Figure 1)
0.6 1.5
DOI Output Rise Time t
R
PP = X, 20% to 80% VDD, R
L
= 5kΩ,
C
L
= 100pF, (Figure 2)
0.9 2 µs
DOI Output Fall Time t
F
PP=high, 80% to 20% VDD, VDD = 24V,
R
L
= 5kΩ, C
L
= 100pF (Figure 2)
0.65 2
µs
PP=low, 80% to 20% VDD, VDD = 24V,
R
L
= 47Ω, C
L
= 100pF (Figure 2)
1
PROPAGATION DELAY (DOI toDOI_LVL)
Propagation Delay LH t
PDL_LH
DOI_EN = low, delay from DOI rising to
5V to DI_LVL low (Figure 3)
2.7 5 µs
Propagation Delay LH DI t
PDL_LH_DI
DOI _EN = high, delay from DOI rising to
8V to DI_LVL low
1.1 µs
Propagation Delay HL t
PDL_HL
DOI _EN = low, delay from DOI falling to
3.5V to DI_LVL high
0.9 8 µs
Propagation Delay HL DI t
PDL_HL_DI
DOI _EN = high, delay from DOI falling to
5.5V to DI_LVL high
0.9 µs
GLITCH REJECTION (IN)
Pulse Length of Rejected
Glitch
t
FPL_GF
0 80 ns
Glitch Filter Delay Time t
D_GF
140 300 ns
FAULT DETECTION (OV_VDD, FAULT)
OV_VDD Threshold V
TH_OV_VDD
DI_EN = low, relative to V
DD
0.22 V
OVLO_VDD Debounce Time TD
OVLO_VDD
DI_EN = low 200 µs
OVLO_VDD Output Leakage I
LK_OV_VDD_
0 < I
OV
< VDD -1 +1 µA
FAULT Output Leakage I
LK_FAULT
0 < I
FAULT
< 5V -1 +1 µA
MAX14914 High-Side Switch with Settable Current-Limiting,
Push-Pull Driver Option and Digital Input Conguration
www.maximintegrated.com
Maxim Integrated
│
5
Electrical Characteristics (continued)
