ADG2128 Data Sheet
Rev. D | Page 8 of 28
ADG2108 Limit at T
, T
Parameter
1
Conditions Min Max Unit Description
t
Standard mode 1000 ns t
, rise time of SCL signal
Fast mode 20 + 0.1 C
300 ns
High speed mode
2
C
= 100 pF maximum 10 40 ns
C
= 400 pF maximum 20 80 ns
t
Standard mode 1000 ns t
, rise time of SCL signal after a repeated start
Fast mode 20 + 0.1 C
300 ns condition and after an acknowledge bit
High speed mode
C
= 100 pF maximum 10 80 ns
C
= 400 pF maximum 20 160 ns
t
Standard mode 300 ns t
, fall time of SCL signal
Fast mode 20 + 0.1 C
300 ns
High speed mode
2
C
= 100 pF maximum 10 40 ns
C
= 400 pF maximum 20 80 ns
t
Fast mode 0 50 ns Pulse width of suppressed spike
High speed mode
2
0 10 ns
1
Guaranteed by initial characterization. All values measured with input filtering enabled. C
B
refers to capacitive load on the bus line; t
R
and t
F
are measured between
0.3 V
DD
and 0.7 V
DD
.
2
High speed I
2
C is available only in -HS models.
3
A device must provide a data hold time for SDA to bridge the undefined region of the SCL falling edge.
TIMING DIAGRAM
P
S
S
P
SDA
SCL
S = START CONDITION
P = STOP CONDITION
t
7
t
6
t
4
t
2
t
11
t
12
t
1
t
3
t
5
t
6
t
10
t
8
t
9
05464-002
Figure 2. Timing Diagram for 2-Wire Serial Interface