Data Sheet ADG2128
Rev. D | Page 19 of 28
SERIAL INTERFACE
The ADG2128 is controlled via an I
2
C-compatible serial bus.
The parts are connected to this bus as a slave device (no clock
is generated by the switch).
HIGH SPEED I
2
C INTERFACE
In addition to standard and full speed I
2
C, the ADG2188 also
supports the high speed (3.4 MHz) I
2
C interface. Only the -HS
models provide this added performance. See the Ordering
Guide for details.
SERIAL BUS ADDRESS
The ADG2128 has a 7-bit slave address. The four MSBs are
hard coded to 1110, and the three LSBs are determined by the
state of Pin A0, Pin A1, and Pin A2. By offering the facility to
hardware configure Pin A0, Pin A1, and Pin A2, up to eight
of these devices can be connected to a single serial bus.
The 2-wire serial bus protocol operates as follows:
1. The master initiates data transfer by establishing a start
condition, defined as when a high-to-low transition on the
SDA line occurs while SCL is high. This indicates that an
address/data stream follows. All slave peripherals connected
to the serial bus respond to the start condition and shift in
the next eight bits, consisting of a 7-bit address (MSB first)
plus an R/
W
bit that determines the direction of the data
transfer, that is, whether data is written to or read from the
slave device.
2. The peripheral whose address corresponds to the trans-
mitted address responds by pulling the SDA line low
during the ninth clock pulse, known as the acknowledge
bit. At this stage, all other devices on the bus remain idle
while the selected device waits for data to be written to or
read from its serial register. If the R/
W
bit is 1 (high), the
master reads from the slave device. If the R/
W
bit is 0
(low), the master writes to the slave device.
3. Data is transmitted over the serial bus in sequences of
nine clock pulses: eight data bits followed by an acknowl-
edge bit from the receiver of the data. Transitions on the
SDA line must occur during the low period of the clock
signal, SCL, and remain stable during the high period of
SCL, because a low-to-high transition when the clock is
high can be interpreted as a stop signal.
4. When all data bits have been read or written, a stop
condition is established by the master. A stop condition
is defined as a low-to-high transition on the SDA line
while SCL is high. In write mode, the master pulls the SDA
line high during the 10th clock pulse to establish a stop
condition. In read mode, the master issues a no acknowledge
for the ninth clock pulse (that is, the SDA line remains
high). The master then brings the SDA line low before the
10th clock pulse and then high during the 10th clock pulse
to establish a stop condition.
Refer to Figure 33 and Figure 34 for a graphical explanation
of the serial data transfer protocol.
