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MC74AC377DW

P1-P3P4-P6P7-P9
© Semiconductor Components Industries, LLC, 2015
March, 2015 − Rev. 10
1 Publication Order Number:
MC74AC377/D
MC74AC377, MC74ACT377
Octal D Flip-Flop with
Clock Enable
The MC74AC377/74ACT377 has eight edge-triggered, D-type
flip-flops with individual D inputs and Q outputs. The common
buffered Clock (CP) input loads all flip-flops simultaneously, when
the Clock Enable (CE
) is LOW. The register is fully edge-triggered.
The state of each D input, one setup time before the LOW-to-HIGH
clock transition, is transferred to the corresponding flip-flop’s Q
output. The CE
input must be stable only one setup time prior to the
LOW-to-HIGH clock transition for predictable operation.
Features
• Ideal for Addressable Register Applications
• Clock Enable for Address and Data Synchronization Applications
• Eight Edge-Triggered D Flip-Flops
• Buffered Common Clock
• Outputs Source/Sink 24 mA
• See MC74AC273 for Master Reset Version
• See MC74AC373 for Transparent Latch Version
• See MC74AC374 for 3-State Version
• ACT377 Has TTL Compatible Inputs
• MSL = 1 for all Surface Mount
• Chip Complexity: 292 FETs or 73 Gates
• These are Pb−Free Devices
1920 18 17 16 15 14
21 34567
V
CC
13
8
12
9
11
10
O
7
D
7
D
6
O
6
O
5
D
5
D
4
O
4
CP
CE
O
0
D
0
D
1
O
1
O
2
D
2
D
3
O
3
GND
Figure 1. Pinout: 20−Lead Packages Conductors
(Top View)
PIN NAMES
PIN FUNCTION
D
0
−D
7
Data Inputs
CE Clock Enable (Active LOW)
Q
0
−Q
7
Data Outputs
CP Clock Pulse Input
Figure 2. Logic Symbol
O
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
CP
CE
www.onsemi.com
SOIC−20W
DW SUFFIX
CASE 751D
TSSOP−20
DT SUFFIX
CASE 948E
1
1
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
ORDERING INFORMATION
See general marking information in the device marking
section on page 7 of this data sheet.
DEVICE MARKING INFORMATION
MC74AC377, MC74ACT377
www.onsemi.com
2
MODE SELECT-FUNCTION TABLE
Operating Mode
Inputs Outputs
CP CE D
n
Q
n
Load ′1′ L H H
Load ′0′ L L L
Hold (Do Nothing)
H X No Change
X H X No Change
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW-to-HIGH Clock Transition
Please note that this diagram is provided only for the understanding of
logic operations and should not be used to estimate propagation delays.
Figure 3. Logic Diagram
DQ
CP
DQ
CP
DQ
CP
DQ
CP
DQ
CP
DQ
CP
DQ
CP
DQ
CP
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
O
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7
CE
CP
MC74AC377, MC74ACT377
www.onsemi.com
3
MAXIMUM RATINGS
Symbol Parameter Value Unit
V
CC
DC Supply Voltage (Referenced to GND) −0.5 to +7.0 V
V
IN
DC Input Voltage (Referenced to GND) −0.5 to V
CC
+0.5 V
V
OUT
DC Output Voltage (Referenced to GND) (Note 1) −0.5 to V
CC
+0.5 V
I
IK
DC Input Diode Current ±20 mA
I
OK
DC Output Diode Current ±50 mA
I
OUT
DC Output Sink/Source Current ±50 mA
I
CC
DC Supply Current, per Output Pin ±50 mA
I
GND
DC Ground Current, per Output Pin ±100 mA
T
STG
Storage Temperature Range *65 to )150
_C
T
L
Lead temperature, 1 mm from Case for 10 Seconds 260
_C
T
J
Junction Temperature Under Bias 140
_C
q
JA
Thermal Resistance (Note 2) SOIC
TSSOP
65.8
110.7
_C/W
MSL Moisture Sensitivity Level 1
F
R
Flammability Rating Oxygen Index: 30% − 35% UL 94 V−0 @ 0.125 in
V
ESD
ESD Withstand Voltage Human Body Model (Note 3)
Machine Model (Note 4)
Charged Device Model (Note 5)
> 2000
> 200
> 1000
V
I
Latchup
Latchup Performance Above V
CC
and Below GND at 85_C (Note 6)
±100 mA
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. I
OUT
absolute maximum rating must be observed.
2. The package thermal impedance is calculated in accordance with JESD 51−7.
3. Tested to EIA/JESD22−A114−A.
4. Tested to EIA/JESD22−A115−A.
5. Tested to JESD22−C101−A.
6. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Typ Max Unit
V
CC
Supply Voltage
′AC 2.0 5.0 6.0
V
′ACT 4.5 5.0 5.5
V
in
, V
out
DC Input Voltage, Output Voltage (Ref. to GND) 0 − V
CC
V
t
r
, t
f
Input Rise and Fall Time (Note 7)
′AC Devices except Schmitt Inputs
V
CC
@ 3.0 V − 150 −
V
CC
@ 4.5 V − 40 − ns/V
V
CC
@ 5.5 V − 25 −
t
r
, t
f
Input Rise and Fall Time (Note 8)
′ACT Devices except Schmitt Inputs
V
CC
@ 4.5 V − 10 −
ns/V
V
CC
@ 5.5 V − 8.0 −
T
A
Operating Ambient Temperature Range −40 25 85 °C
I
OH
Output Current − High − − −24 mA
I
OL
Output Current − Low − − 24 mA
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
7. V
in
from 30% to 70% V
CC
; see individual Data Sheets for devices that differ from the typical input rise and fall times.
8. V
in
from 0.8 V to 2.0 V; see individual Data Sheets for devices that differ from the typical input rise and fall times.
P1-P3P4-P6P7-P9

MC74AC377DW

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Manufacturer:
ON Semiconductor
Description:
IC FF D-TYPE SNGL 8BIT 20SOIC
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