LTC3890-2
13
38902f
OPERATION
(Refer to the Functional Diagram)
Light Load Current Operation (Burst Mode Operation,
Pulse-Skipping or Forced Continuous Mode)
(PLLIN/MODE Pin)
The LTC3890-2 can be enabled to enter high efficiency
Burst Mode operation, constant frequency pulse-skipping
mode, or forced continuous conduction mode at low load
currents. To select Burst Mode operation, tie the PLLIN/
MODE pin to a DC voltage below 0.8V (e.g., SGND). To
select forced continuous operation, tie the PLLIN/MODE
pin to INTV
CC
. To select pulse-skipping mode, tie the
PLLIN/MODE pin to a DC voltage greater than 1.2V and
less than INTV
CC
– 1.3V.
When a controller is enabled for Burst Mode operation, the
minimum peak current in the inductor is set to approxi-
mately 25% of the maximum sense voltage even though
the voltage on the ITH pin indicates a lower value. If the
average inductor current is higher than the load current,
the error amplifier, EA, will decrease the voltage on the
ITH pin. When the ITH voltage drops below 0.425V, the
internal sleep signal goes high (enabling sleep mode)
and both external MOSFETs are turned off. The ITH pin is
then disconnected from the output of the EA and parked
at 0.450V.
In sleep mode, much of the internal circuitry is turned off,
reducing the quiescent current that the LTC3890-2 draws.
If one channel is shut down and the other channel is in
sleep mode, the LTC3890-2 draws only 50µA of quiescent
current. If both channels are in sleep mode, the LTC3890-
2 draws only 60µA of quiescent current. In sleep mode,
the load current is supplied by the output capacitor. As
the output voltage decreases, the EAs output begins to
rise. When the output voltage drops enough, the ITH pin
is reconnected to the output of the EA, the sleep signal
goes low, and the controller resumes normal operation
by turning on the top external MOSFET on the next cycle
of the internal oscillator.
When a controller is enabled for Burst Mode operation, the
inductor current is not allowed to reverse. The reverse cur-
rent comparator, IR, turns off the bottom external MOSFET
just before the inductor current reaches zero, preventing
it from reversing and going negative. Thus, the controller
operates in discontinuous operation.
In forced continuous operation or clocked by an external
clock source to use the phase-locked loop (see Frequency
Selection and Phase-Locked Loop section), the induc-
tor current is allowed to reverse at light loads or under
large transient conditions. The peak inductor current is
determined by the voltage on the ITH pin, just as in normal
operation. In this mode, the efficiency at light loads is lower
than in Burst Mode operation. However, continuous opera-
tion has the advantage of lower output voltage ripple and
less interference to audio circuitry. In forced continuous
mode, the output ripple is independent of load current.
When the PLLIN/MODE pin is connected for pulse-skipping
mode, the LTC3890-2 operates in PWM pulse-skipping
mode at light loads. In this mode, constant frequency
operation is maintained down to approximately 1% of
designed maximum output current. At very light loads, the
current comparator, ICMP, may remain tripped for several
cycles and force the external top MOSFET to stay off for
the same number of cycles (i.e., skipping pulses). The
inductor current is not allowed to reverse (discontinuous
operation). This mode, like forced continuous operation,
exhibits low output ripple as well as low audio noise and
reduced RF interference as compared to Burst Mode
operation. It provides higher low current efficiency than
forced continuous mode, but not nearly as high as Burst
Mode operation.
Frequency Selection and Phase-Locked Loop
(FREQ and PLLIN/MODE Pins)
The selection of switching frequency is a trade-off between
efficiency and component size. Low frequency opera-
tion increases efficiency by reducing MOSFET switching
losses, but requires larger inductance and/or capacitance
to maintain low output ripple voltage.
The switching frequency of the LTC3890-2’s controllers
can be selected using the FREQ pin.
If the PLLIN/MODE pin is not being driven by an external
clock source, the FREQ pin can be tied to SGND, tied to
INTV
CC
or programmed through an external resistor. Tying
FREQ to SGND selects 350kHz while tying FREQ to INTV
CC
selects 535kHz. Placing a resistor between FREQ and SGND
allows the frequency to be programmed between 50kHz
and 900kHz, as shown in Figure 10.
LTC3890-2
14
38902f
OPERATION
(Refer to the Functional Diagram)
A phase-locked loop (PLL) is available on the LTC3890-2
to synchronize the internal oscillator to an external clock
source that is connected to the PLLIN/MODE pin. The
LTC3890-2’s phase detector adjusts the voltage (through
an internal lowpass filter) of the VCO input to align the
turn-on of controller 1’s external top MOSFET to the ris-
ing edge of the synchronizing signal. Thus, the turn-on
of controller 2’s external top MOSFET is 180 degrees out
of phase to the rising edge of the external clock source.
The VCO input voltage is prebiased to the operating fre-
quency set by the FREQ pin before the external clock is
applied. If prebiased near the external clock frequency,
the PLL loop only needs to make slight changes to the
VCO input in order to synchronize the rising edge of the
external clock’s to the rising edge of TG1. The ability to
prebias the loop filter allows the PLL to lock-in rapidly
without deviating far from the desired frequency.
The typical capture range of the phase-locked loop is from
approximately 55kHz to 1MHz, with a guarantee to be
between 75kHz and 850kHz. In other words, the LTC3890-
2’s PLL is guaranteed to lock to an external clock source
whose frequency is between 75kHz and 850kHz.
The typical input clock thresholds on the PLLIN/MODE
pin are 1.6V (rising) and 1.1V (falling).
When synchronized to an external clock using the PLLIN/
MODE pin, the LTC3890-2 operates in pulse-skipping
mode at light loads.
PolyPhase Applications (CLKOUT and PHASMD Pins)
The LTC3890-2 features two pins (CLKOUT and PHASMD)
that allow other controller ICs to be daisy-chained with the
LTC3890-2 in PolyPhase applications. The clock output
signal on the CLKOUT pin can be used to synchronize
additional power stages in a multiphase power supply
solution feeding a single, high current output or multiple
separate outputs. The PHASMD pin is used to adjust the
phase of the CLKOUT signal as well as the relative phases
between the two internal controllers, as summarized in
Table 1. The phases are calculated relative to the zero
degrees phase being defined as the rising edge of the top
gate driver output of controller 1 (TG1).
Table 1
V
PHASMD
CONTROLLER 2 PHASE CLKOUT PHASE
GND 180° 60°
Floating 180° 90°
INTV
CC
240° 120°
Power Good (PGOOD1 and PGOOD2) Pins
Each PGOOD pin is connected to an open drain of an internal
N-channel MOSFET. The MOSFET turns on and pulls the
PGOOD pin low when the corresponding V
FB
pin voltage is
not within ±10% of the 0.8V reference voltage. The PGOOD
pin is also pulled low when the corresponding RUN pin
is low (shut down). When the V
FB
pin voltage is within
the ±10% requirement, the MOSFET is turned off and the
pin is allowed to be pulled up by an external resistor to a
source no greater than 6V.
Theory and Benefits of 2-Phase Operation
Why the need for 2-phase operation? Up until the 2-phase
family, constant-frequency dual switching regulators
operated both channels in phase (i.e., single phase
operation). This means that both switches turned on at
the same time, causing current pulses of up to twice the
amplitude of those for one regulator to be drawn from the
input capacitor and battery. These large amplitude current
pulses increased the total RMS current flowing from the
input capacitor, requiring the use of more expensive input
capacitors and increasing both EMI and losses in the input
capacitor and battery.
LTC3890-2
15
38902f
OPERATION
(Refer to the Functional Diagram)
With 2-phase operation, the two channels of the dual
switching regulator are operated 180 degrees out-of-phase.
This effectively interleaves the current pulses drawn by the
switches, greatly reducing the overlap time where they add
together. The result is a significant reduction in total RMS
input current, which in turn allows less expensive input
capacitors to be used, reduces shielding requirements for
EMI and improves real world operating efficiency.
Figure 1 compares the input waveforms for a representative
single-phase dual switching regulator to the LTC3890-2
2-phase dual switching regulator. An actual measurement of
the RMS input current under these conditions shows that
2-phase operation dropped the input current from 2.53A
RMS
to 1.55A
RMS
. While this is an impressive reduction in itself,
remember that the power losses are proportional to I
RMS
2
,
meaning that the actual power wasted is reduced by a fac-
tor of 2.66. The reduced input ripple voltage also means
less power is lost in the input power path, which could
include batteries, switches, trace/connector resistances
and protection circuitry. Improvements in both conducted
and radiated EMI also directly accrue as a result of the
reduced RMS input current and voltage.
Of course, the improvement afforded by 2-phase opera-
tion is a function of the dual switching regulators relative
duty cycles which, in turn, are dependent upon the input
voltage V
IN
(Duty Cycle = V
OUT
/V
IN
). Figure 2 shows how
the RMS input current varies for single-phase and 2-phase
operation for 3.3V and 5V regulators over a wide input
voltage range.
It can readily be seen that the advantages of 2-phase op-
eration are not just limited to a narrow operating range,
for most applications is that 2-phase operation will reduce
the input capacitor requirement to that for just one chan-
nel operating at maximum current and 50% duty cycle.
Figure 2. RMS Input Current Comparison
INPUT VOLTAGE (V)
0
INPUT RMS CURRENT (A)
3.0
2.5
2.0
1.5
1.0
0.5
0
10 20 30 40
38902 F02
SINGLE PHASE
DUAL CONTROLLER
2-PHASE
DUAL CONTROLLER
V
O1
= 5V/3A
V
O2
= 3.3V/3A
I
IN(MEAS)
= 2.53A
RMS
I
IN(MEAS)
= 1.55A
RMS
38902 F01
5V SWITCH
20V/DIV
3.3V SWITCH
20V/DIV
INPUT CURRENT
5A/DIV
INPUT VOLTAGE
500mV/DIV
Figure 1. Input Waveforms Comparing Single-Phase (a) and 2-Phase (b) Operation for Dual Switching Regulators
Converting 12V to 5V and 3.3V at 3A Each. The Reduced Input Ripple with the 2-Phase Regulator Allows
Less Expensive Input Capacitors, Reduces Shielding Requirements for EMI and Improves Efficiency

LTC3890HUH-2#TRPBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators 60V Low IQ, Dual Output Synchronous Step-Down Controller
Lifecycle:
New from this manufacturer.
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