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LTC3406ABES5-2#TRMPBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18
LTC3406AB-2
10
3406ab2fa
For more information www.linear.com/LTC3406AB-2
Typically, once the ESR requirement for C
OUT
has been met,
the RMS current rating generally far exceeds the I
RIPPLE(P-P)
requirement. The output ripple DV
OUT
is determined by:
DV
OUT
≅ DI
L
ESR +
1
8fC
OUT
where f = operating frequency, C
OUT
= output capacitance
and DI
L
= ripple current in the inductor. For a fixed output
voltage, the output ripple is highest at maximum input
voltage since DI
L
increases with input voltage.
Aluminum electrolytic and dry tantalum capacitors are both
available in surface mount configurations. In the case of
tantalum, it is critical that the capacitors are surge tested
for use in switching power supplies. An excellent choice is
the AVX TPS series of surface mount tantalum. These are
specially constructed and tested for low ESR so they give
the lowest ESR for a given volume. Other capacitor types
include Sanyo POSCAP, Kemet T510 and T495 series, and
Sprague 593D and 595D series. Consult the manufacturer
for other specific recommendations.
Using Ceramic Input and Output Capacitors
Higher values, lower cost ceramic capacitors are now
becoming available in smaller case sizes. Their high
ripple current, high voltage rating and low ESR make
them ideal for switching regulator applications. Because
the LTC3406AB-2’s control loop does not depend on
the output capacitor’s ESR for stable operation, ceramic
capacitors can be used freely to achieve very low output
ripple and small circuit size.
However, care must be taken when ceramic capacitors
are used at the input and the output. When a ceramic
capacitor is used at the input and the power is supplied
by a wall adapter through long wires, a load step at the
output can induce ringing at the input, V
IN
. At best, this
ringing can couple to the output and be mistaken as loop
instability. At worst, a sudden inrush of current through
the long wires can potentially cause a voltage spike at V
IN
,
large enough to damage the part.
When choosing the input and output ceramic capacitors,
choose the X5R or X7R dielectric formulations. These
dielectrics have the best temperature and voltage char
-
acteristics of all the ceramics for a given value and size.
Output V
oltage Programming
In the adjustable version
, the output voltage is set by a
resistive divider according to the following formula:
V
OUT
= 0.6V 1+
R2
R1
(2)
The external resistive divider is connected to the output,
allowing remote voltage sensing as shown in Figure 1.
applicaTions inForMaTion
V
FB
GND
LTC3406AB-2
0.6V ≤ V
OUT
≤ 5.5V
R2
R1
3406AB2 F01
Figure 1. Setting the LTC3406AB-2 Output Voltage
Efficiency Considerations
The efficiency of a switching regulator is equal to the output
power divided by the input power times 100%. It is often
useful to analyze individual losses to determine what is
limiting the efficiency and which change would produce
the most improvement. Efficiency can be expressed as:
Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percent
-
age of input power.
LTC3406AB-2
11
3406ab2fa
For more information www.linear.com/LTC3406AB-2
Although all dissipative elements in the circuit produce
losses, two main sources usually account for most of the
losses in LTC3406AB-2 circuits: V
IN
quiescent current and
I
2
R losses. The V
IN
quiescent current loss dominates the
efficiency loss at very low load currents whereas the I
2
R
loss dominates the efficiency loss at medium to high load
currents. In a typical efficiency plot, the efficiency curve at
very low load currents can be misleading since the actual
power lost is of no consequence as illustrated in Figure 2.
2. I
2
R losses are calculated from the resistances of the
internal switches, R
SW
, and external inductor R
L
. In
continuous mode, the average output current flowing
through inductor L is “chopped” between the main
switch and the synchronous switch. Thus, the series
resistance looking into the SW pin is a function of both
top and bottom MOSFET R
DS(ON)
and the duty cycle
(DC) as follows:
R
SW
= (R
DS(ON)TOP
)(DC) + (R
DS(ON)BOT
)(1 – DC)
The R
DS(ON)
for both the top and bottom MOSFETs can
be obtained from the Typical Performance Character-
istics curves. Thus, to obtain I
2
R losses, simply add
R
SW
to R
L
and multiply the result by the square of the
average output current.
Other losses including C
IN
and C
OUT
ESR dissipative losses
and inductor core losses generally account for less than
2% total additional loss.
Thermal Considerations
In most applications the LTC3406AB-2 does not dissipate
much heat due to its high efficiency. But, in applications
where the LTC3406AB-2 is running at high ambient tem
-
perature with low supply voltage and high duty cycles,
such as in dropout, the heat dissipated may exceed the
maximum junction temperature of the part. If the junction
temperature reaches approximately 150°C, both power
switches will be turned off and the SW node will become
high impedance.
To avoid the LTC3406AB-2 from exceeding the maximum
junction temperature, the user will need to do some thermal
analysis. The goal of the thermal analysis is to determine
whether the power dissipated exceeds the maximum
junction temperature of the part. The temperature rise is
given by:
T
R
= (P
D
)(θ
JA
)
where P
D
is the power dissipated by the regulator and θ
JA
is the thermal resistance from the junction of the die to
the ambient temperature.
applicaTions inForMaTion
Figure 2. Power Loss vs Load Current
1. The V
IN
quiescent current is due to two components:
the DC bias current as given in the electrical charac-
teristics and the internal main switch and synchronous
switch gate charge currents
.
The gate charge current
results from switching the gate capacitance of the
internal power MOSFET switches. Each time the gate
is switched from high to low to high again, a packet of
charge, dQ, moves from V
IN
to ground. The resulting
dQ/dt is the current out of V
IN
that is typically larger
than the DC bias current. In continuous mode, I
GATECHG
= f(Q
T
+ Q
B
) where Q
T
and Q
B
are the gate charges of
the internal top and bottom switches. Both the DC bias
and gate charge losses are proportional to V
IN
and thus
their effects will be more pronounced at higher supply
voltages.
OUTPUT CURRENT (mA)
0.001
POWER LOSS (W)
0.01
0.1
1
0.1 10 100 1000
3406AB2 F02
0.0001
1
V
IN
= 3.6V
V
OUT
= 1.2V
V
OUT
= 1.8V
V
OUT
= 2.5V
LTC3406AB-2
12
3406ab2fa
For more information www.linear.com/LTC3406AB-2
The junction temperature, T
J
, is given by:
T
J
= T
A
+ T
R
where T
A
is the ambient temperature.
As an example, consider the LTC3406AB-2 in dropout
at an input voltage of 2.7V, a load current of 600mA and
an ambient temperature of 70°C. From the typical per
-
formance graph of switch resistance, the R
DS(ON)
of the
P-channel switch at 70°C is approximately 0.27
W. There-
fore, power dissipated by the part is:
P
D
= I
LOAD
2
• R
DS(ON)
= 97.2mW
For the SOT-23 package, the θ
JA
is 250°C/W. Thus, the
junction temperature of the regulator is:
T
J
= 70°C + (0.0972)(250) = 94.3°C
which is below the maximum junction temperature of
125°C.
Note that at higher supply voltages, the junction tempera
-
ture is lower due to reduced switch resistance (R
DS(ON)
).
Checking Transient Response
The regulator loop response can be checked by looking
at the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, V
OUT
immediately shifts by an amount
equal to (DI
LOAD
• ESR), where ESR is the effective series
resistance of C
OUT
. DI
LOAD
also begins to charge or dis-
charge C
OUT
, which generates a feedback error signal. The
regulator loop then acts to return V
OUT
to its steady-state
value. During this recovery time V
OUT
can be monitored
for overshoot or ringing that would indicate a stability
problem. For a detailed explanation of switching control
loop theory, see Application Note 76.
A second, more severe transient is caused by switching
in loads with large (>1µF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in paral
-
lel with C
OUT
, causing a rapid drop in V
OUT
. No regulator
can deliver enough current to prevent this problem if the
load switch resistance is low and it is driven quickly. The
only solution is to limit the rise time of the switch drive
so that the load rise time is limited to approximately
(25 •
C
LOAD
). Thus, a 10µF capacitor charging to 3.3V
would require a 250µs rise time, limiting the charging
current to about 130mA.
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3406AB-2. These items are also illustrated graphically
in Figures 3 and 4. Check the following in your layout:
1. The power traces, consisting of the GND trace, the SW
trace, the V
OUT
trace, and the V
IN
trace should be kept
short, direct and wide.
2. Does the V
FB
pin connect directly to the feedback
resistors? The resistive divider R1/R2 must be
connected between the (+) plate of C
OUT
and ground.
3. Does C
IN
connect to V
IN
as closely as possible? This
capacitor provides the AC current to the internal power
MOSFETs.
4. Keep the switching node, SW, away from the sensitive
V
FB
node.
5. Keep the (–) plates of C
IN
, C
OUT
and the IC ground as
close as possible.
applicaTions inForMaTion
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18

LTC3406ABES5-2#TRMPBF

Mfr. #:
Buy LTC3406ABES5-2#TRMPBF
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators 1.5MHz, 600mA Synch Step Down Regulator
Lifecycle:
New from this manufacturer.
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