MAX5187BEEG+ Datasheet MAX5187BEEG+, MAX5190BEEG, MAX5190BEEG-T | P10-P12

MAX5187/MAX5190

8-Bit, 40MHz, Current/Voltage-Output DACs

10 ______________________________________________________________________________________

(POWER-DOWN SELECT)

DACEN

(DAC ENABLE)

POWER-DOWN MODE OUTPUT STATE

0 0 Standby

MAX5187 High-Z

MAX5190 AGND

0 1 Wake-Up Last state prior to standby mode

1 X Shutdown

MAX5187 High-Z

MAX5190 AGND

Table 1. Power-Down Mode Selection

X = Don’t care

External Reference

To disable the MAX5187/MAX5190’s internal reference,

connect REN to DV

. A temperature-stable external ref-

erence may now be applied to drive the REFO pin to set

the full-scale output (Figure 3). Choose a reference that

can supply at least 150µA to drive the bias circuit that

generates the cascode current for the current array. For

improved accuracy and drift performance, choose a volt-

age reference with a fixed output voltage, such as the

+1.2V, 25ppm/°C MAX6520 bandgap reference.

Standby Mode

To enter the lower power standby mode, connect the

digital inputs PD and DACEN to DGND. In standby,

both the reference and the control amplifier are active

with the current array inactive. To exit this condition,

DACEN must be pulled high with PD held at DGND.

Both the MAX5187 and MAX5190 typically require 50µs

to wake up and allow both the outputs and the refer-

ence to settle.

Shutdown Mode

For lowest power consumption, the MAX5187/MAX5190

provide a power-down mode in which the reference,

control amplifier, and current array are inactive and the

DAC’s supply current is reduced to 1µA. To enter this

mode, connect PD to DV

. To return to active mode,

connect PD to DGND and DACEN to DV

. About 50µs

are required for the parts to leave shutdown mode and

settle to their outputs’ values prior to shutdown.

Timing Information

Figure 4 shows a detailed timing diagram for the

MAX5187/MAX5190. With each high transition of the

clock, the input latch is loaded with the digital value set

by bits D7 through D0. The content of the input latch is

then shifted to the DAC register, and the output

updates at the rising edge of the next clock.

CLK

D0–D7

OUT N - 1

N - 1

N + 1

CLK

Figure 4. Timing Diagram

MAX5187/MAX5190

8-Bit, 40MHz, Current/Voltage-Output DACs

______________________________________________________________________________________ 11

Outputs

The MAX5187 output is designed to supply full-scale

output currents of 1mA into 400Ω loads in parallel with

a capacitive load of 5pF. The MAX5190 features inte-

grated 400Ω resistors that restore the array current to

proportional, differential voltages of 400mV. These dif-

ferential output voltages can then be used to drive a

balun transformer or a low-distortion, high-speed oper-

ational amplifier to convert the differential voltage into a

single-ended voltage.

Applications Information

Static and Dynamic

Performance Definitions

Integral Nonlinearity

Integral nonlinearity (INL) (Figure 5a) is the deviation of

the values on an actual transfer function from either a

best-straight-line fit (closest approximation to the actual

transfer curve) or a line drawn between the endpoints

of the transfer function once offset and gain errors have

been nullified. For a DAC, the deviations are measured

every single step.

Differential Nonlinearity

Differential nonlinearity (DNL) (Figure 5b) is the differ-

ence between an actual step height and the ideal value

of 1LSB. A DNL error specification of less than 1LSB

guarantees no missing codes and a monotonic transfer

function.

Offset Error

Offset error (Figure 5c) is the difference between the

ideal and the actual offset point. For a DAC, the offset

point is the step value when the digital input is zero.

This error affects all codes by the same amount and

can usually be compensated by trimming.

Figure 5a. Integral Nonlinearity

Figure 5b. Differential Nonlinearity

Figure 5c. Offset Error

Figure 5d. Gain Error

000 010001 011 100 101 110

AT STEP

011 (1/2 LSB )

AT STEP

001 (1/4 LSB )

111

DIGITAL INPUT CODE

ANALOG OUTPUT VALUE

000 010001 011 100 101

DIFFERENTIAL LINEARITY

ERROR (-1/4 LSB)

DIFFERENTIAL

LINEARITY ERROR (+1/4 LSB)

1 LSB

DIGITAL INPUT CODE

ANALOG OUTPUT VALUE

000 010001 011

ACTUAL

DIAGRAM

IDEAL DIAGRAM

ACTUAL

OFFSET

POINT

OFFSET ERROR

(+1 1/4 LSB)

IDEAL OFFSET

POINT

DIGITAL INPUT CODE

ANALOG OUTPUT VALUE

000 101100 110 111

IDEAL DIAGRAM

GAIN ERROR

(-1 1/4 LSB)

IDEAL FULL-SCALE OUTPUT

ACTUAL

FULL-SCALE

OUTPUT

DIGITAL INPUT CODE

ANALOG OUTPUT VALUE

MAX5187/MAX5190

8-Bit, 40MHz, Current/Voltage-Output DACs

12 ______________________________________________________________________________________

Gain Error

Gain error (Figure 5d) is the difference between the

ideal and the actual full-scale output voltage on the

transfer curve, after nullifying the offset error. This error

alters the slope of the transfer function and corre-

sponds to the same percentage error in each step.

Settling Time

Settling time is the amount of time required from the start

of a transition until the DAC output settles its new output

value to within the converter’s specified accuracy.

Digital Feedthrough

Digital feedthrough is the noise generated on a DAC’s

output when any digital input transitions. Proper board

layout and grounding will significantly reduce this

noise, but there will always be some feedthrough

caused by the DAC itself.

Total Harmonic Distortion

Total harmonic distortion (THD) is the ratio of the RMS

sum of the input signal’s first four harmonics to the fun-

damental itself. This is expressed as:

where V

is the fundamental amplitude, and V

through

are the amplitudes of the 2nd- through 5th-order

harmonics.

Spurious-Free Dynamic Range

Spurious-free dynamic range (SFDR) is the ratio of RMS

amplitude of the fundamental (maximum signal compo-

nent) to the RMS value of the next-largest distortion com-

ponent.

Differential to Single-Ended Conversion

The MAX4108 low-distortion, high-input bandwidth

amplifier may be used to generate a voltage from the

array current output of the MAX5187. The differential

voltage across OUTP and OUTN is converted into a

single-ended voltage by designing an appropriate

operational amplifier configuration (Figure 6).

I/Q Reconstruction in a QAM Application

The low-distortion performance of two MAX5187/

MAX5190s supports analog reconstruction of in-phase

(I) and quadrature (Q) carrier components typically

used in quadrature amplitude modulation (QAM) archi-

tectures, where two separate buses carry the I and Q

data. A QAM signal is both amplitude and phase mod-

ulated, created by summing two independently modu-

lated carriers of identical frequency but different phase

(90° phase difference).

THD 20 log

VVVV

=×

+++













400Ω*

REN AGNDDGND

+5V

-5V

402Ω

OUTP

CLK

OUTN

0.1µF

SET

OUTPUT

MAX5187

MAX5190

10µF

+3V

0.1µF

REFR

REFO

D0–D7

10µF

CREF

0.1µF

MAX4108

*400Ω RESISTORS INTERNAL TO MAX5190 ONLY.

**MAX5187 ONLY

Figure 6. Differential to Single-Ended Conversion Using a Low-Distortion Amplifier

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15

MAX5187BEEG+

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Digital to Analog Converters - DAC 8-Bit High Speed DAC

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