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AD9058AKD

P1-P3P4-P6P7-P9P10-P12
REV.
–3–
AD9058
Test AD9058AJD/AJJ AD9058AKD/AKJ
Parameter Temp Level Min Typ Max Min Typ Max Unit
DYNAMIC PERFORMANCE
Transient Response 25°CV 2 2 ns
Overvoltage Recovery Time 25°CV 2 2 ns
Effective Number of Bits (ENOB)
3
Analog Input @ 2.3 MHz 25°C I 7.7 7.2 7.7 Bits
@ 10.3 MHz 25°C I 7.4 7.1 7.4 Bits
Signal-to-Noise Ratio
3
Analog Input @ 2.3 MHz 25°C I 48 45 48 dB
@ 10.3 MHz 25°C I 46 44 46 dB
Signal-to-Noise Ratio
3
(Without Harmonics)
Analog Input @ 2.3 MHz 25°C I 48 46 48 dB
@ 10.3 MHz 25°C I 47 45 47 dB
Second Harmonic Distortion
Analog Input @ 2.3 MHz 25°C I 58 48 58 dBc
@ 10.3 MHz 25°C I 58 48 58 dBc
Third Harmonic Distortion
Analog Input @ 2.3 MHz 25°C I 58 50 58 dBc
@ 10.3 MHz 25°C I 58 50 58 dBc
Crosstalk Rejection
4
25°C IV 60 48 60 dBc
DIGITAL OUTPUTS
Logic “1” Voltage (I
OH
= 2 mA) Full VI 2.4 2.4 V
Logic “0” Voltage (I
OL
= 2 mA) Full VI 0.4 0.4 V
POWER SUPPLY
5
+V
S
Supply Current Full VI 127 154 127 154 mA
–V
S
Supply Current Full VI 27 38 27 38 mA
Power Dissipation Full VI 770 960 770 960 mW
NOTES
1
For applications in which +V
S
may be applied before –V
S
, or +V
S
current is not limited to 500 mA, a reverse-biased clamping diode should be inserted between
ground and –V
S
to prevent destructive latch up. See section entitled “Using the AD9058.”
2
To achieve guaranteed conversion rate, connect each data output to ground through a 2 k Ω pull-down resistor.
3
SNR performance limits for the 48-lead DIP “D” package are 1 dB less than shown. ENOB limits are degraded by 0.3 dB. SNR and ENOB measured with
analog input signal 1 dB below full scale at specified frequency.
4
Crosstalk rejection measured with full-scale signals of different frequencies (2.3 MHz and 3.5 MHz) applied to each channel. With both signals synchronously
encoded at 40 MSPS, isolation of the undesired frequency is measured with an FFT.
5
Applies to both A/Ss and includes internal ladder dissipation.
Specifications subject to change without notice.
E
REV.
AD9058
–4–
EXPLANATION OF TEST LEVELS
Test Level
I. 100% production tested.
II. 100% production tested at 25°C, and sample tested at
specified temperatures.
III. Sample tested only.
IV. Parameter is guaranteed by design and characterization
testing.
V. Parameter is a typical value only.
VI. All devices are 100% production tested at 25°C. 100%
production tested at temperature extremes for extended
temperature devices; sample tested at temperature
extremes for commercial/industrial devices.
DIGITAL BITS
+V
S
Equivalent Digital Outputs
5V
ENCODE
13k⍀
Equivalent Encode Circuit
AD9058
ENCODE**
A
IN
**
–V
REF
+V
S
–V
S
–5.2V
+5V
GROUND
COMP
+V
REF
+V
INT
D
0
–D
7
*+V
S
** INDICATES EACH PIN IS CONNECTED THROUGH 100⍀
* INDICATES EACH PIN IS CONNECTED THROUGH 2k⍀
0.1␮F
Burn-In Connections
ABSOLUTE MAXIMUM RATINGS
1
Analog Input . . . . . . . . . . . . . . . . . . . . . . . . –1.5 V to +2.5 V
+V
S
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V
–V
S
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.8 V to –6 V
2
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +V
S
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Voltage Reference Current . . . . . . . . . . . . . . . . . . . . . . 53 mA
+V
REF
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 V
–V
REF
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –1.5 V
Operating Temperature Range
AD9058AJD/AJJ/AKD/AKJ . . . . . . . . . . . . . . . 0°C to 70°C
Maximum Junction Temperature
3
AD9058AJD/AJJ/AKD/AKJ . . . . . . . . . . . . . . . . . . . 150°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300°C
NOTES
1
Absolute maximum ratings are limiting values to be applied individually, and
beyond which the serviceability of the circuit may be impaired. Functional
operability is not necessarily implied. Exposure to absolute maximum rating
conditions for an extended period of time may affect device reliability.
2
For applications in which +V
S
may be applied before –V
S
, or +V
S
current is
not limited to 500 mA, a reverse-biased clamping diode should be inserted
between ground and –V
S
to prevent destructive latch up. See section entitled
“Using the AD9058.”
3
Typical thermal impedances: 44-lead hermetic J-leaded ceramic package: θ
JA
= 86.4°C/W;
θ
JC
= 24.9°C/W; 48-lead hermetic: DIP θ
JA
= 40°C/W; θ
JC
= 12°C/W.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9058 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
E
REV.
AD9058
–5–
7
17
18
28
39
29
GROUND
GROUND
6
+V
REF
COMP
NC
ENCODE
GROUND
GROUND
GROUND
NC
GROUND
ENCODE
D
7
(MSB)
40
TOP VIEW
(Not to Scale)
AD9058
NC = NO CONNECT
GROUND
+V
INT
+V
REF
+V
S
A
IN
A
IN
+V
S
+V
S
+V
S
–V
REF
–V
S
–V
REF
–V
S
+V
S
–V
S
–V
S
+V
S
D
7
(MSB)
D
0
(LSB)
D
0
(LSB)
D
6
D
5
D
3
D
4
D
2
D
1
D
1
D
2
D
3
D
4
D
5
D
6
AD9058AJJ/AKJ Pinouts
TOP VIEW
(Not to Scale)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
AD9058
NC = NO CONNECT
GROUND D
7
(MSB)
ENCODE D
6
+V
S
D
5
GROUND D
4
–V
REF
D
3
–V
S
D
2
NC D
1
A
IN
D
0
(LSB)
+V
S
GROUND
GROUND –V
S
+V
REF
GROUND
COMP +V
S
+V
INT
+V
S
+V
REF
GROUND
GROUND –V
S
+V
S
GROUND
A
IN
D
0
(LSB)
NC D
1
D
2
–V
REF
D
3
GROUND D
4
+V
S
D
5
ENCODE D
6
GROUND D
7
(MSB)
–V
S
AD9058AJD/AKD Pinouts
PIN FUNCTION DESCRIPTIONS
J-Lead Ceramic DIP
Pin Number Pin Number
ADC-A ADC-B Mnemonic Function ADC-A ADC-B
343 +V
REF
Top of Internal Voltage Reference Ladder 14 11
4 42 GROUND Analog Ground Return 15 10
541 +V
S
Positive 5 V Analog Supply Voltage 16 9
640 A
IN
Analog Input Voltage 17 8
739 –V
S
Negative 5 V Supply Voltage 19 6
838 –V
REF
Bottom of Internal Voltage Reference Ladder 20 5
937 +V
S
Positive 5 V Digital Supply Voltage 22 3
10 36 ENCODE TTL Compatible Convert Command 23 2
11 35 D
7
(MSB) Most Significant Bit of TTL Digital Output 25 48
12–17 34–29 D
6
–D
1
TTL Compatible Digital Output Bits 26–31 47–42
18 28 D
0
(LSB) Least Significant Bit of TTL Digital Output 32 41
19 27 GROUND Digital Ground Return 21, 24, 33 1, 4, 40
20 26 –V
S
Negative 5 V Supply Voltage 34 39
21 25 GROUND Analog Ground Return 35 38
22 24 +V
S
Positive 5 V Analog Supply Voltage 36 37
COMMON PINS COMMON PINS
1 COMP Connection for External (0.1 μF) 12
Compensation Capacitor
2+V
INT
Internal 2 V Reference; Can Drive 13
+V
REF
for Both ADCs
PIN CONFIGURATIONS
E
P1-P3P4-P6P7-P9P10-P12

AD9058AKD

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Analog to Digital Converters - ADC Dual 8-Bit 50 MSPS
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