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813001AGILF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
DUAL VCXO W/3.3V, 2.5V LVPECL FEMTOCLOCK™ PLL
813001I DATA SHEET
10 REVISION A 3/17/15
Symbol Parameter Test Conditions Minimum Typical Maximum Units
C
V_LOW
Low Varactor Capacitance V
C
= 0V 15 pF
C
V_HIGH
High Varactor Capacitance V
C
= 3.3V 27.4 pF
TABLE 7. VARACTOR PARAMETERS
FORMULAS
()( )
()( )
LowVSLLowVSL
LowVSLLowVSL
Low
CCCCCC
CCCCCC
C
_22_11
_22_11
+++++
++⋅++
=
()( )
()( )
HighVSLHighVSL
HighVSLHighVSL
High
CCCCCC
CCCCCC
C
_22_11
_22_11
+++++
++⋅++
=
• C
Low
is the effective capacitance due to the low varactor capacitance, load capacitance and stray capacitance.
C
Low
determines the high frequency component on the TPR.
• C
High
is the effective capacitance due to the high varactor capacitance, load capacitance and stray capacitance.
C
High
determines the low frequency component on the TPR.
Absolute Pull Range (APR) = Total Pull Range – (Frequency Tolerance + Frequency Stability + Aging)
EXAMPLE CALCULATIONS
Using the tables and fi gures above, we can now calculate
the TPR and APR of the VCXO using the example crystal
parameters. For the numerical example below there were
some assumptions made. First, the stray capacitance (C
S1
,
C
S2
), which is all the excess capacitance due to board parasitic,
is 4pF. Second, the expected lifetime of the project is 5 years;
hence the inaccuracy due to aging is ±15ppm. Third, though
many boards will not require load tuning capacitors (C
L1
, C
L2
),
it is recommended for long-term consistent performance of the
system that two tuning capacitor pads be placed into every
design. Typical values for the load tuning capacitors will range
from 0 to 4pF.
TPR = ±106ppm
APR = 106ppm – (20ppm + 20ppm + 15ppm) = ±51ppm
The example above will ensure a total pull range of
±106 ppm with an APR of ±51ppm. Many times, board
designers may select their own crystal based on their
application. If the application requires a tighter APR, a crystal
with better pullability (C0/C1 ratio) can be used. Also, with
the equations above, one can vary the frequency tolerance,
temperature stability, and aging or shunt capacitance to achieve
the required pullability.
C
Low
=
(0 + 4pƒ + 15pƒ ) · (0 + 4pƒ + 15pƒ )
(0 + 4pƒ + 15pƒ ) · (0 + 4pƒ + 15pƒ )
= 9.5pƒ
C
High
=
(0 + 4pƒ + 27.4pƒ ) · (0 + 4pƒ + 27.4pƒ )
(0 + 4pƒ + 27.4pƒ ) · (0 + 4pƒ + 27.4pƒ )
= 15.7pƒ
⋅
⎟
⎟
⎟
⎟
⎠
⎞
⎟
⎠
⎞
1
2· 220 ·
(1 +
9.5pƒ
4pƒ ) 2· 220 · (1 +
15.7pƒ
4pƒ )
1
–
2
⎜
⎜
⎜
⎜
⎝
⎛
=
TPR
=
= · 10
6
· = 212ppm
REVISION A 3/17/15
813001I DATA SHEET
11 DUAL VCXO W/3.3V, 2.5V LVPECL FEMTOCLOCK™ PLL
FIGURE 4C. CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 4B. CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 4D. CLK/nCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
3.3V
R1
50
R3
50
Zo = 50 Ohm
LVPECL
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
3.3V
Input
R2
50
Zo = 50 Ohm
Input
HiPerClockS
CLK
nCLK
3.3V
R3
125
R2
84
Zo = 50 Ohm
3.3V
R4
125
LVPECL
R1
84
3.3V
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both V
SWING
and V
OH
must meet the
V
PP
and V
CMR
input requirements. Figures 4A to4E show inter-
face examples for the HiPerClockS CLK/nCLK input driven by
the most common driver types. The input interfaces suggested
here are examples only. Please consult with the vendor of the
FIGURE 4A. CLK/nCLK INPUT DRIVEN BY
ICS HIPERCLOCKS LVHSTL DRIVER
driver component to confi rm the driver termination requirements.
For example in Figure 4A, the input termination applies for ICS
HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
from another vendor, use their termination recommendation.
1.8V
R2
50
Input
LVHSTL Driver
ICS
HiPerClockS
R1
50
LVHSTL
3.3V
Zo = 50 Ohm
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
FIGURE 4E. CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER WITH AC COUPLE
Zo = 50 Ohm
R3
125
HiPerClockS
CLK
nCLK
3.3V
R5
100 - 200
3.3V
R2
84
3.3V
R6
100 - 200
Input
R5,R6 locate near the driver pin.
Zo = 50 Ohm
R1
84
R4
125
C2
LVPECL
C1
DUAL VCXO W/3.3V, 2.5V LVPECL FEMTOCLOCK™ PLL
813001I DATA SHEET
12 REVISION A 3/17/15
TERMINATION FOR 3.3V LVPECL OUTPUT
The clock layout topology shown below is a typical termination
for LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, termi-
nating resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
drive 50Ω transmission lines. Matched impedance techniques
FIGURE 5B. LVPECL OUTPUT TERMINATION
FIGURE 5A. LVPECL OUTPUT TERMINATION
should be used to maximize operating frequency and minimize
signal distortion. Figures 5A and 5B show two different layouts
which are recommended only as guidelines. Other suitable clock
layouts may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
INPUTS:
CRYSTAL INPUT:
For applications not requiring the use of the crystal oscillator
input, both XTAL_IN and XTAL_OUT can be left fl oating. Though
not required, but for additional protection, a 1kΩ resistor can be
tied from XTAL_IN to ground.
CLK I
NPUT:
For applications not requiring the use of a clock input, it can be
left fl oating. Though not required, but for additional protection, a
1kΩ resistor can be tied from the CLK input to ground.
CLK/nCLK I
NPUT:
For applications not requiring the use of the differential input,
both CLK and nCLK can be left fl oating. Though not required,
but for additional protection, a 1kΩ resistor can be tied from
CLK to ground.
LVCMOS C
ONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
VC input pin - do not fl oat, must be biased.
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
OUTPUTS:
LVPECL OUTPUT
All unused LVPECL outputs can be left fl oating. We recommend
that there is no trace attached. Both sides of the differential
output pair should either be left fl oating or terminated.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20

813001AGILF

Mfr. #:
Buy 813001AGILF
Manufacturer:
IDT
Description:
Clock Generators & Support Products 1 LVPECL OUTPUT DUAL VCXO/FEMTOCLOCK
Lifecycle:
New from this manufacturer.
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