XC18V00 Series In-System-Programmable Configuration PROMs
DS026 (v5.2) January 11, 2008 www.xilinx.com
Product Specification 14
Reset and Power-On Reset Activation
At power up, the device requires the V
CCINT
power supply to
rise monotonically to the nominal operating voltage within
the specified V
CCINT
rise time. If the power supply cannot
meet this requirement, then the device might not perform
power-on reset properly. During the power-up sequence,
OE/RESET
is held Low by the PROM.
Once the required supplies have reached their respective
POR (Power On Reset) thresholds, the OE/RESET
release
is delayed (T
OER
minimum) to allow more margin for the
power supplies to stabilize before initiating configuration.
The OE/RESET
pin is connected to an external pull-up
resistor and also to the target FPGA's INIT_B pin. For
systems utilizing slow-rising power supplies, an additional
power monitoring circuit can be used to delay the target
configuration until the system power reaches minimum
operating voltages by holding the OE/RESET
pin Low.
When OE/RESET
is released, the FPGA’s INIT_B pin is
pulled High, allowing the FPGA's configuration sequence to
begin. If the power drops below the power-down threshold
(V
CCPD
), the PROM resets and OE/RESET is again held
Low until the after the POR threshold is reached.
OE/RESET
polarity is not programmable. These power-up
requirements are shown graphically in Figure 9.
For a fully powered Platform Flash PROM, a reset occurs
whenever OE/RESET
is asserted (Low) or CE is deasserted
(High). The address counter is reset, CEO
is driven High, and
the remaining outputs are placed in a high-Z state.
Standby Mode
The PROM enters a low-power standby mode whenever CE
is asserted High. The address is reset. The output remains
in a high-Z state regardless of the state of the OE input.
JTAG pins TMS, TDI and TDO can be in a high-Z state or
High. See Ta ble 7 .
When using the FPGA DONE signal to drive the PROM CE
pin High to reduce standby power after configuration, an
external pull-up resistor should be used. Typically a 330Ω
pull-up resistor is used, but refer to the appropriate FPGA
data sheet for the recommended DONE pin pull-up value. If
the DONE circuit is connected to an LED to indicate FPGA
configuration is complete, and also connected to the PROM
CE
pin to enable low-power standby mode, then an external
buffer should be used to drive the LED circuit to ensure valid
transitions on the PROMs CE
pin. If low-power standby
mode is not required for the PROM, then the CE
pin should
be connected to ground.
5V Tolerant I/Os
The I/Os on each re-programmable PROM are fully 5V tolerant
even through the core power supply is 3.3V. This allows 5V
CMOS signals to connect directly to the PROM inputs without
damage. In addition, the 3.3V V
CCINT
power supply can be
applied before or after 5V signals are applied to the I/Os. In
mixed 5V/3.3V/2.5V systems, the user pins, the core power
supply (V
CCINT
), and the output power supply (V
CCO
) can have
power applied in any order. This makes the PROM devices
immune to power supply sequencing issues.
X-Ref Target - Figure 9
Figure 9: V
CCINT
Power-Up Requirements
T
OER
V
CCINT
V
CCPOR
V
CCPD
200 µs ramp
50 ms ramp
T
OER
T
RST
TIME (ms)
A slow-ramping V
CCINT
supply may still
be below the minimum operating
voltage when OE/RESET is released.
In this case, the configuration
sequence must be delayed until both
V
CCINT
and V
CCO
have reached their
recommended operating conditions.
Recommended Operating Range
Delay or Restart
Configuration
ds026_20_032504
