74ABT574CMTCX

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74ABT574
DC Electrical Characteristics
(SOIC Package)
Note 5: Max number of outputs defined as (n). n 1 data inputs are driven 0V to 3V. One output at LOW. Guaranteed, but not tested.
Note 6: Max number of outputs defined as (n). n
1 data inputs are driven 0V to 3V. One output HIGH. Guaranteed, but not tested.
Note 7: Max number of data inputs (n) switching. n
1 inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (V
ILD
), 0V to threshold (V
IHD
).
Guaranteed, but not tested.
AC Electrical Characteristics
(SOIC and SSOP Package)
AC Operating Requirements
Symbol Parameter Min Typ Max Units
V
CC
Conditions
C
L
50 pF, R
L
500
V
OLP
Quiet Output Maximum Dynamic V
OL
0.7 1.0 V 5.0 T
A
25 C (Note 5)
V
OLV
Quiet Output Minimum Dynamic V
OL
1.5 1.1 V 5.0 T
A
25 C (Note 5)
V
OHV
Minimum HIGH Level Dynamic Output Voltage 2.5 3.0 V 5.0 T
A
25 C (Note 6)
V
IHD
Minimum HIGH Level Dynamic Input Voltage 2.0 1.6 V 5.0 T
A
25 C (Note 7)
V
ILD
Maximum LOW Level Dynamic Input Voltage 1.2 0.8 V 5.0 T
A
25 C (Note 7)
Symbol Parameter
T
A
25 C T
A
55 C to 125 C T
A
40 C to 85 C
Units
V
CC
5.0V V
CC
4.5V to 5.5V V
CC
4.5V to 5.5V
C
L
50 pF C
L
50 pF C
L
50 pF
Min Typ Max Min Max Min Max
f
MAX
Maximum Clock Frequency 150 200 150 150 MHz
t
PLH
Propagation Delay 2.0 3.2 5.0 1.5 7.0 2.0 5.0
ns
t
PHL
CP to O
n
2.0 3.3 5.0 1.5 7.4 2.0 5.0
t
PZH
Output Enable Time 1.5 3.1 5.3 1.0 6.5 1.5 5.3
ns
t
PZL
1.5 3.1 5.3 1.0 7.2 1.5 5.3
t
PHZ
Output Disable Time 1.5 3.6 5.4 1.0 7.2 1.5 5.4
ns
t
PLZ
1.5 3.4 5.4 1.0 6.7 1.5 5.4
Symbol Parameter
T
A
25 C T
A
55 C to 125 C T
A
40 C to 85 C
Units
V
CC
5.0V V
CC
4.5V to 5.5V V
CC
4.5V to 5.5V
C
L
50 pF C
L
50 pF C
L
50 pF
Min Max Min Max Min Max
t
S
(H) Setup Time, HIGH 1.0 1.5 1.0
ns
t
S
(L) or LOW D
n
to CP 1.5 2.0 1.5
t
H
(H) Hold Time, HIGH 1.0 2.0 1.0
ns
t
H
(L) or LOW D
n
to CP 1.0 2.0 1.0
t
W
(H) Pulse Width, CP, 3.0 3.3 3.0
ns
t
W
(L) HIGH or LOW 3.0 3.3 3.0
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74ABT574
Extended AC Electrical Characteristics
(SOIC Package)
Note 8: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.).
Note 9: This specification is guaranteed but not tested. The limits represent propagation delay with 250 pF load capacitors in place of the 50 pF load capac-
itors in the standard AC load. This specification pertains to single output switching only.
Note 10: This specification is guaranteed but not tested. The limits represent propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.) with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load.
Note 11: The 3-STATE Delay Times are dominated by the RC network (500
, 250 pF) on the output and has been excluded from the datasheet.
Skew (Note 12)
(SOIC package)
Note 12: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.).
Note 13: This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load
capacitors in the standard AC load.
Note 14: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device.
The specification applies to any outputs switching HIGH-to-LOW (t
OSHL
), LOW-to-HIGH (t
OSLH
), or any combination switching LOW-to-HIGH and/or HIGH-
to-LOW (t
OST
). This specification is guaranteed but not tested.
Note 15: This describes the difference between the delay of the LOW-to-HIGH and the HIGH-to-LOW transition on the same pin. It is measured across all
the outputs (drivers) on the same chip, the worst (largest delta) number is the guaranteed specification. This specification is guaranteed but not tested.
Note 16: Propagation delay variation for a given set of conditions (i.e., temperature and V
CC
) from device to device. This specification is guaranteed but not
tested.
Capacitance
Note 17: C
OUT
is measured at frequency f 1 MHz, per MIL-STD-883, Method 3012.
Symbol Parameter
T
A
40 C to 85 CT
A
40 C to 85 C T
A
40 C to 85 C
Units
V
CC
4.5V to 5.5V V
CC
4.5V to 5.5V V
CC
4.5V to 5.5V
C
L
50 pF C
L
250 pF C
L
250 pF
8 Outputs Switching (Note 9) 8 Outputs Switching
(Note 8) (Note 10)
Min Max Min Max Min Max
t
PLH
Propagation Delay 1.5 5.7 2.0 7.8 2.0 10.0
ns
t
PHL
CP to O
n
1.5 5.7 2.0 7.8 2.0 10.0
t
PZH
Output Enable Time 1.5 6.2 2.0 8.0 2.0 10.5
ns
t
PZL
1.5 6.2 2.0 8.0 2.0 10.5
t
PHZ
Output Disable Time 1.0 5.5
(Note 11) (Note 11) ns
t
PLZ
1.0 5.5
Symbol Parameter
T
A
40 C to 85 C T
A
40 C to 85 C
Units
V
CC
4.5V–5.5V V
CC
4.5V–5.5V
C
L
50 pF C
L
250 pF
8 Outputs Switching 8 Outputs Switching
(Note 12) (Note 13)
Max Max
t
OSHL
Pin to Pin Skew
1.0 1.8 ns
(Note 14) HL Transitions
t
OSLH
Pin to Pin Skew
1.0 1.8 ns
(Note 14) LH Transitions
t
PS
Duty Cycle
1.8 4.3 ns
(Note 15) LHHL Skew
t
OST
Pin to Pin Skew
2.0 4.3 ns
(Note 14) LH/HL Transitions
t
PV
Device to Device Skew
2.5 4.6 ns
(Note 16) LH/HL Transitions
Symbol Parameter Typ Units
Conditions
T
A
25 C
C
IN
Input Capacitance 5.0 pF V
CC
0V
C
OUT
(Note 17) Output Capacitance 9.0 pF V
CC
5.0V
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74ABT574
AC Loading
*Includes jig and probe capacitance
FIGURE 1. Standard AC Test Load
FIGURE 2. V
M
1.5V
Input Pulse Requirements
FIGURE 3. Test Input Signal Requirements
AC Waveforms
FIGURE 4. Propagation Delay Waveforms for
Inverting and Non-Inverting Functions
FIGURE 5. Propagation Delay,
Pulse Width Waveforms
FIGURE 6. 3-STATE Output HIGH
and LOW Enable and Disable Times
FIGURE 7. Setup Time, Hold Time
and Recovery Time Waveforms
Amplitude Rep. Rate t
W
t
r
t
f
3.0V 1 MHz 500 ns 2.5 ns 2.5 ns

74ABT574CMTCX

Mfr. #:
Manufacturer:
ON Semiconductor / Fairchild
Description:
Flip Flops Oct D-Type Flip-Flop
Lifecycle:
New from this manufacturer.
Delivery:
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