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74ABT574CSCX

P1-P3P4-P6P7-P9P10-P10
© 2005 Fairchild Semiconductor Corporation DS011511 www.fairchildsemi.com
November 1992
Revised March 2005
74ABT574 Octal D-Type Flip-Flop with 3-STATE Outputs
74ABT574
Octal D-Type Flip-Flop with 3-STATE Outputs
General Description
The ABT574 is an octal flip-flop with a buffered common
Clock (CP) and a buffered common Output Enable (OE
).
The information presented to the D inputs is stored in the
flip-flops on the LOW-to-HIGH Clock (CP) transition.
The device is functionally identical to the ABT374 but has
broadside pinouts.
Features
■ Inputs and outputs on opposite sides of package
allowing easy interface with microprocessors
■ Useful as input or output port for microprocessors
■ Functionally identical to ABT374
■ 3-STATE outputs for bus-oriented applications
■ Output sink capability of 64 mA, source capability
of 32 mA
■ Guaranteed output skew
■ Guaranteed multiple output switching specifications
■ Output switching specified for both 50 pF and
250 pF loads
■ Guaranteed simultaneous switching, noise level and
dynamic threshold performance
■ Guaranteed latchup protection
■ High impedance glitch free bus loading during entire
power up and power down cycle
■ Non-destructive hot insertion capability
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Connection Diagram
Pin Descriptions
Order Number Package Number Package Description
74ABT574CSC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74ABT574CSJ M20D Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ABT574CMSA MSA20 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
74ABT574CMTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pin Names Description
D
0
–D
7
Data Inputs
CP Clock Pulse Input (Active Rising Edge)
OE
3-STATE Output Enable Input (Active LOW)
O
0
–O
7
3-STATE Outputs
www.fairchildsemi.com 2
74ABT574
Functional Description
The ABT574 consists of eight edge-triggered flip-flops with
individual D-type inputs and 3-STATE true outputs. The
buffered clock and buffered Output Enable are common to
all flip-flops. The eight flip-flops will store the state of their
individual D inputs that meet the setup and hold times
requirements on the LOW-to-HIGH Clock (CP) transition.
With the Output Enable (OE
) LOW, the contents of the
eight flip-flops are available at the outputs. When OE
is
HIGH, the outputs are in a high impedance state. Opera-
tion of the OE
input does not affect the state of the flip-
flops.
Function Table
H HIGH Voltage Level
L
LOW Voltage Level
X
Immaterial
Z
High Impedance
LOW-to-HIGH Transition
NC
No Change
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Inputs Internal Outputs Function
OE
CP D Q O
H H or L L NC Z Hold
H H or L H NC Z Hold
H
L L Z Load
H
H H Z Load
L
L L L Data Available
L
H H H Data Available
L H or L L NC NC No Change in Data
L H or L H NC NC No Change in Data
3 www.fairchildsemi.com
74ABT574
Absolute Maximum Ratings(Note 1) Recommended Operating
Conditions
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Note 3: Guaranteed, but not tested.
Note 4: For 8-bit toggling, I
CCD
0.8 mA/MHz.
Storage Temperature 65 C to 150 C
Ambient Temperature under Bias
55 C to 125 C
Junction Temperature under Bias
55 C to 150 C
V
CC
Pin Potential to Ground Pin 0.5V to 7.0V
Input Voltage (Note 2)
0.5V to 7.0V
Input Current (Note 2)
30 mA to 5.0 mA
Voltage Applied to Any Output
in the Disabled or
Power-Off State
0.5V to 5.5V
in the HIGH State
0.5V to V
CC
Current Applied to Output
in LOW State (Max) twice the rated I
OL
(mA)
DC Latchup Source Current
500 mA
Over Voltage Latchup (I/O) 10V
Free Air Ambient Temperature
40 C to 85 C
Supply Voltage
4.5V to 5.5V
Minimum Input Edge Rate (
V/ t)
Data Input 50 mV/ns
Enable Input 20 mV/ns
Clock Input 100 mV/ns
Symbol Parameter Min Typ Max Units
V
CC
Conditions
V
IH
Input HIGH Voltage 2.0 V Recognized HIGH Signal
V
IL
Input LOW Voltage 0.8 V Recognized LOW Signal
V
CD
Input Clamp Diode Voltage 1.2 V Min I
IN
18 mA
V
OH
Output HIGH Voltage 2.5 V Min I
OH
3 mA
2.0 V Min I
OH
32 mA
V
OL
Output LOW Voltage 0.55 I
OL
64 mA
I
IH
Input HIGH Current 1
A Max
V
IN
2.7V (Note 3)
1 V
IN
V
CC
I
BVI
Input HIGH Current Breakdown Test 7 A Max V
IN
7.0V
I
IL
Input LOW Current 1
A Max
V
IN
0.5V (Note 3)
1 V
IN
0.0V
V
ID
Input Leakage Test 4.75 V 0.0 I
ID
1.9 A
All Other Pins Grounded
I
OZH
Output Leakage Current 10 A 0 5.5V V
OUT
2.7V; OE 2.0V
I
OZL
Output Leakage Current 10 A 0 5.5V V
OUT
0.5V; OE 2.0V
I
OS
Output Short-Circuit Current 100 275 mA Max V
OUT
0.0V
I
CEX
Output High Leakage Current 50 A Max V
OUT
V
CC
I
ZZ
Bus Drainage Test 100 A 0.0 V
OUT
5.5V; All Other GND
I
CCH
Power Supply Current 50 A Max All Outputs HIGH
I
CCL
Power Supply Current 30 mA Max All Outputs LOW
I
CCZ
Power Supply Current 50 A Max OE V
CC
All Others at V
CC
or GND
I
CCT
Additional I
CC
/Input Outputs Enabled 2.5 mA V
I
V
CC
2.1V
Outputs 3-STATE 2.5 mA Max Enable Input V
I
V
CC
2.1V
Outputs 3-STATE 2.5 mA Data Input V
I
V
CC
2.1V
All Others at V
CC
or GND
I
CCD
Dynamic I
CC
No Load mA/
Max
Outputs Open, OE GND,
(Note 3) 0.30 MHz One Bit Toggling (Note 4),
50% Duty Cycle
P1-P3P4-P6P7-P9P10-P10

74ABT574CSCX

Mfr. #:
Buy 74ABT574CSCX
Manufacturer:
ON Semiconductor / Fairchild
Description:
Flip Flops Oct D-Type Flip-Flop
Lifecycle:
New from this manufacturer.
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