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CAT24M01WI-GT3

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18
© Semiconductor Components Industries, LLC, 2012
May, 2018 − Rev. 4
1 Publication Order Number:
CAT24M01/D
CAT24M01
EEPROM Serial 1-Mb I
2
C
Description
The CAT24M01 is a EEPROM Serial 1−Mb I
2
C, internally
organized as 131,072 words of 8 bits each.
It features a 256−byte page write buffer and supports the Standard
(100 kHz), Fast (400 kHz) and Fast−Plus (1 MHz) I
2
C protocol.
Write operations can be inhibited by taking the WP pin High (this
protects the entire memory).
External address pins make it possible to address up to four
CAT24M01 devices on the same bus.
On−Chip ECC (Error Correction Code) makes the device suitable
for high reliability applications.
Features
• Supports Standard, Fast and Fast−Plus I
2
C Protocol
• 1.8 V to 5.5 V Supply Voltage Range
• 256−Byte Page Write Buffer
• Hardware Write Protection for Entire Memory
• Schmitt Triggers and Noise Suppression Filters on I
2
C Bus Inputs
(SCL and SDA)
• Low Power CMOS Technology
• 1,000,000 Program/Erase Cycles
• 100 Year Data Retention
• Industrial and Extended Temperature Range
• 8−pin, SOIC, TSSOP and 8−pad UDFN Packages
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Figure 1. Functional Symbol
SDA
SCL
WP
CAT24M01
V
CC
V
SS
A
2
, A
1
www.onsemi.com
PIN CONFIGURATION
SDA
WP
V
CC
V
SS
A
2
A
1
NC
1
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
ORDERING INFORMATION
SOIC−8
W SUFFIX
CASE 751BD
SOIC−8
X SUFFIX
CASE 751BE
SCL
SOIC (W, X), TSSOP (Y),
UDFN (HU5)
TSSOP−8
Y SUFFIX
CASE 948AL
Device AddressA
1
, A
2
Serial DataSDA
Serial ClockSCL
Write ProtectWP
Power SupplyV
CC
GroundV
SS
FunctionPin Name
PIN FUNCTION
For the location of Pin 1, please consult the
corresponding package drawing.
UDFN−8
HU5 SUFFIX
CASE 517BU
SOIC−8 WIDE
X SUFFIX
CASE 751BE
CAT24M01
www.onsemi.com
2
M0L
ALL
YM
G
M0L = Specific Device Code
A = Assembly Location Code
LL = Assembly Lot Number
Y = Year
M = Month
G = Pb−Free Package
MARKING DIAGRAMS
24M01A = Specific Device Code
A = Assembly Location
Y = Production Year (Last Digit)
M = Production Month (1−9, O, N, D)
XXX = Last Three Digits of
XXX = Assembly Lot Number
24M01A
AYMXXX
(SOIC−8) (UDFN−8)
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameters Ratings Units
Storage Temperature –65 to +150 °C
Voltage on any Pin with Respect to Ground (Note 1) –0.5 to +6.5 V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. The DC input voltage on any pin should not be lower than −0.5 V or higher than V
CC
+ 0.5 V. During transitions, the voltage on any pin may
undershoot to no less than −1.5 V or overshoot to no more than V
CC
+ 1.5 V, for periods of less than 20 ns.
Table 2. RELIABILITY CHARACTERISTICS (Note 2)
Symbol Parameter Min Units
N
END
(Notes 3, 4) Endurance 1,000,000 Program/Erase Cycles
T
DR
Data Retention 100 Years
2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
3. Test Condition: Page Mode, V
CC
= 5 V, 25°C.
4. The device uses ECC (Error Correction Code) logic with 6 ECC bits to correct one bit error in 4 data bytes. Therefore, when a single byte
has to be written, 4 bytes (including the ECC bits) are re-programmed. It is recommended to write by multiple of 4 bytes in order to benefit
from the maximum number of write cycles.
Table 3. D.C. OPERATING CHARACTERISTICS
V
CC
= 1.8 V to 5.5 V, T
A
= −40°C to +85°C and V
CC
= 2.5 V to 5.5 V, T
A
= −40°C to +125°C, unless otherwise specified.
Symbol
Parameter Test Conditions Min Max Units
I
CCR
Read Current Read, f
SCL
= 400 kHz / 1 MHz 1 mA
I
CCW
Write Current
V
CC
= 1.8 V 3.5
mA
V
CC
= 5.5 V 5.0
I
SB
Standby Current All I/O Pins at GND or V
CC
T
A
= −40°C to +85°C 2 mA
T
A
= −40°C to +125°C 5
I
L
I/O Pin Leakage Pin at GND or V
CC
T
A
= −40°C to +85°C 1 mA
T
A
= −40°C to +125°C 2
V
IL1
Input Low Voltage 2.5 V ≤ V
CC
≤ 5.5 V −0.5 0.3 V
CC
V
V
IL2
Input Low Voltage 1.8 V ≤ V
CC
< 2.5 V −0.5 0.25 V
CC
V
V
IH1
Input High Voltage 2.5 V ≤ V
CC
≤ 5.5 V 0.7 V
CC
V
CC
+ 0.5 V
V
IH2
Input High Voltage 1.8 V ≤ V
CC
< 2.5 V 0.75 V
CC
V
CC
+ 0.5 V
V
OL1
Output Low Voltage V
CC
≥ 2.5 V, I
OL
= 3.0 mA 0.4 V
V
OL2
Output Low Voltage V
CC
< 2.5 V, I
OL
= 1.0 mA 0.2 V
CAT24M01
www.onsemi.com
3
Table 4. PIN IMPEDANCE CHARACTERISTICS
V
CC
= 1.8 V to 5.5 V, T
A
= −40°C to +85°C and V
CC
= 2.5 V to 5.5 V, T
A
= −40°C to +125°C, unless otherwise specified.
Symbol
Parameter Conditions Max Units
C
IN
(Note 5) SDA I/O Pin Capacitance V
IN
= 0 V 8 pF
C
IN
(Note 5) Input Capacitance (other pins) V
IN
= 0 V 6 pF
I
WP
, I
A
(Note 6) WP Input Current, Address Input Current (A
1
, A
2
)
V
IN
< V
IH
, V
CC
= 5.5 V 75 mA
V
IN
< V
IH
, V
CC
= 3.3 V 50
V
IN
< V
IH
, V
CC
= 1.8 V 25
V
IN
> V
IH
2
5. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
6. When not driven, the WP, A
1
, A
2
pins are pulled down to GND internally. For improved noise immunity, the internal pull−down is relatively
strong; therefore the external driver must be able to supply the pull−down current when attempting to drive the input HIGH. To conserve power,
as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x V
CC
), the strong pull−down reverts to a weak current source.
Table 5. A.C. CHARACTERISTICS (Note 7)
V
CC
= 1.8 V to 5.5 V, T
A
= −40°C to +85°C and V
CC
= 2.5 V to 5.5 V, T
A
= −40°C to +125°C, unless otherwise specified.
Symbol
Parameter
Standard
V
CC
= 1.8 V − 5.5 V
Fast
V
CC
= 1.8 V − 5.5 V
Fast−Plus
V
CC
= 2.5 V − 5.5 V
T
A
= −405C to +855C
Units
Min Max Min Max Min Max
F
SCL
Clock Frequency 100 400 1,000 kHz
t
HD:STA
START Condition Hold Time 4 0.6 0.25
ms
t
LOW
Low Period of SCL Clock 4.7 1.3 0.45
ms
t
HIGH
High Period of SCL Clock 4 0.6 0.40
ms
t
SU:STA
START Condition Setup Time 4.7 0.6 0.25
ms
t
HD:DAT
Data In Hold Time 0 0 0
ms
t
SU:DAT
Data In Setup Time 250 100 50 ns
t
R
(Note 8) SDA and SCL Rise Time 1,000 300 100 ns
t
F
(Note 8) SDA and SCL Fall Time 300 300 100 ns
t
SU:STO
STOP Condition Setup Time 4 0.6 0.25
ms
t
BUF
Bus Free Time Between
STOP and START
4.7 1.3 0.5
ms
t
AA
SCL Low to Data Out Valid 3.5 0.9 0.40
ms
t
DH
Data Out Hold Time 50 50 50 ns
T
i
(Note 8) Noise Pulse Filtered at SCL
and SDA Inputs
50 50 50 ns
t
SU:WP
WP Setup Time 0 0 0
ms
t
HD:WP
WP Hold Time 2.5 2.5 1
ms
t
WR
Write Cycle Time 5 5 5 ms
t
PU
(Notes 8, 9) Power-up to Ready Mode 0.1 0.1 0.1 ms
7. Test conditions according to “A.C. Test Conditions” table.
8. Tested initially and after a design or process change that affects this parameter.
9. t
PU
is the delay between the time V
CC
is stable and the device is ready to accept commands.
Table 6. A.C. TEST CONDITIONS
Input Levels 0.2 x V
CC
to 0.8 x V
CC
Input Rise and Fall Times ≤ 50 ns
Input Reference Levels 0.3 x V
CC
, 0.7 x V
CC
Output Reference Levels 0.5 x V
CC
Output Load Current Source: I
L
= 3 mA (V
CC
≥ 2.5 V); I
L
= 1 mA (V
CC
< 2.5 V); C
L
= 100 pF
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18

CAT24M01WI-GT3

Mfr. #:
Buy CAT24M01WI-GT3
Manufacturer:
ON Semiconductor
Description:
EEPROM 1MB I2C SERIAL EEPROM
Lifecycle:
New from this manufacturer.
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