HMC1031 Data Sheet
Rev. C | Page 10 of 13
APPLICATIONS INFORMATION
Figure 22. Typical Application Diagram
JITTER ATTENUATION
In some cases, reference clocks to the system may come from
external noisy sources with high jitter. The HMC1031 can be
used to attenuate this incoming jitter and distribute a clean
clock in the system. In such a scheme, a narrow loop filter is
selected for the HMC1031. The device frequency locks to the
external VCXO, but the reference jitter is attenuated as defined by
the set loop filter bandwidth. The final output frequency and
phase noise characteristics outside the loop bandwidth is defined
by the phase noise characteristics of the VCXO used. A low
jitter clock reference yields better clocking performance and
better LO performance of the RF PLL VCOs, and improves the
SNR performance of analog-to-digital converters (ADCs) and
digital-to-analog converters (DACs).
FREQUENCY TRANSLATION
The reference clock in a test and measurement system or a
communications system is often a high accuracy OCXO with
excellent long-term stability. In some applications, the OCXO
frequency must be multiplied up to a higher rate to drive the
primary clock inputs in a system. The HMC1031 offers a very
low power, small package and high performance method to
multiply its incoming frequency in 1×, 5×, and 10× rates. Such
multiplication is required because the higher reference clocks
improve phase noise, ADC/DAC signal-to-noise ratio (SNR),
clock generator jitter, and PHY bit error rates (BERs). In this
scheme, the HMC1031 can be connected to an external low cost
VCXO (for example, at 50 MHz or 100 MHz), and lock this
external VCXO to the excellent long-term stability of the OCXO.
LOOP BANDWIDTHS WITH HMC1031
In typical jitter attenuation applications, an incoming reference
clock is frequency locked with a narrow PLL loop bandwidth
such that its incoming noise is filtered out by the PLL and VCXO
combination. The out of band phase noise of the PLL follows
the VCXO that it is locked to. A narrow PLL loop bandwidth
ensures that the output jitter is determined by the VCXO (or
any other type of high quality factor VCO) and not affected by
the spectral noise of the incoming clock beyond the set loop
bandwidth.
To fa c ilitate narrow bandwidth loop filter configurations, the
HMC1031 is designed to have a low charge pump current of
50 µA. This architecture offers advantages in low power consump-
tion and loop filter design. Typically, narrow loop filter
bandwidths require large filter capacitors. Due to the low charge
pump current design of the HMC1031, smaller loop filter capaci-
tor sizes can be used to implement narrow loop filters. Note that
the HMC1031 is designed to operate in loop bandwidths of only
a few kilohertz in its widest loop bandwidth configuration.
USING VCOs/VCXOs WITH NEGATIVE TUNING
SLOPE
In its typical configuration, the HMC1031 works with any
VCO/VCXO that has a positive tuning slope. For any VCO/VCXO
with negative tuning slope, that is, when the frequency decreases
with increasing tuning voltage, connect the loop filter ac ground
to VCC instead of GND.
LOCK DETECTOR
The lock detector measures the arrival times between the divided
VCO edge and reference edge appearing at the phase detector.
When this offset becomes greater than approximately 6 ns, the
lock detector indicates an out of lock condition. Any leakage
current on the CP output causes a phase offset between the two
edges. Due to the relatively small 50 µA charge pump current,
the HMC1031 is sensitive to leakage currents and may indicate
a false out of lock condition if the leakage current from the
charge pump (Pin 7) to ground is too high.
Leakage currents include dc current through the loop filter
capacitors and/or dc current into the VCO tuning voltage pin,
V
TUNE
. It is recommended to use low leakage, loop filter multi-
layer ceramic capacitors (MLCCs) and careful VCO selection to
maximize V
TUNE
resistance. The maximum acceptable leakage is
dependent on the phase detector operating frequency and can
be calculated as follows:
where:
I
LEAKAGE
is the total leakage current in µA.
I
CP
is the charge pump current in µA (set to 50 µA).
t
PD
is the reference frequency period in ns.
Internal delays reduce the available lock detector range from
6 ns to 3 ns.
UP TO 140MHz
NOISY CLOCK
REFERENCE
NARROW LOOP FILTER
UP TO 500MHz
CLEAN CLOCK
SIGNAL
VCXO
VCC
D0
LKDOP
REFIN
1
2
3
4
GND
D1
VCOIN
CP
8
7
6
5
PFD/CP
LKD
1/N
HMC1031
13353-023
