AT87LV52
14
Figure 9. Programming the QuickFlash Memory Figure 10. Verifying the QuickFlash Memory
P1
P2.6
P3.6
P2.0 - P2.4
A0 - A7
ADDR.
0000H/1FFFH
SEE FLASH
PROGRAMMING
MODES TABLE
3-16 MHz
A8 - A12
P0
+5V
P2.7
PGM
DATA
PROG
V/V
IH PP
V
IH
ALE
P3.7
XTAL2 EA
P3.4
RST
PSEN
XTAL
1
GND
V
CC
AT87LV52
RDY/BSY
P1
P2.6
P3.6
P2.0 - P2.4
A0 - A7
ADDR.
0000H/1FFFH
SEE FLASH
PROGRAMMING
MODES TABLE
3-16 MHz
A8 - A12
P0
+5V
P2.7
PGM DATA
(USE 10K
PULLUPS)
V
IH
V
IH
ALE
P3.7
XTAL2 EA
RST
PSEN
XTAL1
GND
V
CC
AT87LV52
QuickFlash Programming and Verification Characteristics
T
A
= 0°C to 70°C, V
CC
= 5.0
±
10%
Symbol Parameter Min Max Units
V
PP
Programming Enable Voltage 11.5 12.5 V
I
PP
Programming Enable Current 1.0 mA
1/t
CLCL
Oscillator Frequency 3 16 MHz
t
AVGL
Address Setup to PROG Low 48t
CLCL
t
GHAX
Address Hold After PROG 48t
CLCL
t
DVGL
Data Setup to PROG Low 48t
CLCL
t
GHDX
Data Hold After PROG 48t
CLCL
t
EHSH
P2.7 (ENABLE) High to V
PP
48t
CLCL
t
SHGL
V
PP
Setup to PROG Low 10 µs
t
GHSL
V
PP
Hold After PROG 10 µs
t
GLGH
PROG Width 1 110 µs
t
AVQV
Address to Data Valid 48t
CLCL
t
ELQV
ENABLE Low to Data Valid 48t
CLCL
t
EHQZ
Data Float After ENABLE 048t
CLCL
t
GHBL
PROG High to BUSY Low 1.0 µs
t
WC
Byte Write Cycle Time 2.0 ms
