PL102-10TI Datasheet PL102-10TC, PL102-10SC-R, PL102-10TI-R | P1-P3

PL102-10

Low Skew Output Buffer

Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 2/5/09 Page 1

FEATURES

 Frequency Range:

− 15 to 170MHz @ 3.3V

− 15 to 145MHz @ 2.5V

 Internal Phase Locked Loop Allows Spread

Spectrum Modulation on Reference Clock to

Pass to Outputs.

 Zero Input to Output Delay

 Less Than 700ps Device to Device Skew

 Less Than 200ps Skew Between Outputs

 Less Than 100ps Cycle to Cycle Jitter

 2.5V or 3.3V Power Supply

 Available in 8-Pin SOP or 6-pin SOT GREEN/ RoHS

Compliant Packages

PIN CONFIGURATION

DESCRIPTION

The PL102-10 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed

clocks and is available in 8-pin SOP or 6-pin SOT23 package. It has two outputs that are synchronized with the

input. The synchronization is established via CLKOUT feed back to the input of the PLL. Since the skew between

the input and output is less than 350 ps, the device acts as a zero delay buffer.

BLOCK DIAGRAM

PLL

REFIN CLKOUT

CLK1

CLK2

1

2

3

4 5

6

7

8REFIN

CLK1

CLK2

CLKOUT

DNC

VDD

DNCGND

SOP-8L

1

2

3 4

5

6

CLK1

GND

REFIN

CLK2

CLKOUT

VDD

SOT23-6L

PL102-10

Low Skew Output Buffer

Micrel Inc. • 2 180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • f ax +1(408) 474-1000 • www.micrel.com Rev 2/5/09 Page 2

PIN DESCRIPTIONS

Name

Pin Number

Type

Description

SOP-8L

SOT23-6L

REFIN

1

3

I

Input reference frequency. Spread spectrum modulation on this

signal will be passed to the output (up to 100kHz SST modul ation).

GND

2

P

Ground Connection.

CLK1

3

1

O

Buffered clock output.

CLK2*

4

6

O

Buffered clock output.

VDD

5

P

2.5V or 3.3V Power Supply connection.

DNC

6, 7

-

Do Not Connect

CLKOUT

8

4

O

Buffered clock output. Internal feed back on this pin.

*Note: If CLK2 is pulled high during startup the device will enter test mode.

ELECTRICAL SPECIFICATIONS

1. Absolute Maximum Ratings

PARAMETERS

SYMBOL

MIN.

MAX.

UNITS

Supply Voltage

V

DD

4.6

V

Input Voltage, dc

V

I

-0.5

V

DD

+0.5

V

Output Voltage, dc

V

O

-0.5

V

DD

+0.5

V

Storage Temperature

T

S

-65

150

C

Ambient Operating Temperature*

T

A

-40

85

C

Junction Temperature

T

J

125

C

Lead Temperature (soldering, 10s)

260

C

Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended perio ds m ay cause permanent damage to the

device and affect product reliability. These conditions represent a stress rating only, and functional operations of the dev ice at these or any other co n-

ditions above the operational limits noted in this specification is no t implied. *Operating temperature is guaranteed by design. Parts are tested to

commercial grade only.

2. Electrical Characteristics

PARAMETERS

SYMBOL

CONDITIONS

MIN.

TYP.

MAX.

UNITS

Supply Voltage

V

DD

2.25

3.63

V

Input Low Voltage

V

IL

0.8

V

Input High Voltage

V

IH

2.0

V

Output Low Voltage

V

OL

I

OL

= 24mA

0.4

V

Output High Voltage

V

OH

I

OH

= 24mA

2.4

V

Supply Current

I

DD

Unloaded outputs at 100MHz,

V

DD

=3.3V.

22

30

mA

PL102-10

Low Skew Output Buffer

Micrel Inc. • 2 180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • f ax +1(408) 474-1000 • www.micrel.com Rev 2/5/09 Page 3

3. Switching Characteristics

PARAMETERS

SYMBOL

CONDITIONS

MIN.

TYP.

MAX.

UNITS

Input/Output Frequency

t1

2.5V/3.3V

15

145/170

MHz

Duty Cycle

DC

Measured at V

DD

/2, C

L

=15pF,

F

ou t

= 100MHz

45

50

55

%

Rise Time

T

r

Measured between 10% and

90%V

DD

, C

L

=15pF

1.2

1.5

ns

Fall Time

T

f

Measured between 90% and

10%, C

L

=15pF

1.2

1.5

ns

Output to Output Skew

T

ske w

All outputs equally loaded,

C

L

=15pF

200

ps

Delay, REF Rising Edge

to CLKOUT Rising Edge

T

dela y

Measured at V

DD

/2

0

350

ps

Device to Device Skew

T

dsk-dsk

Measured at V

DD

/2 on the

CLKOUT pins of devices

0

700

ps

Cycle to Cycle Jitter

T

cyc-c yc

Measured at 100MHz

60

ps

PLL Lock Time

T

loc k

Stable power supply, valid

clock presented on REF pin

1.0

ms

Jitter; Absolute Jitter

T

jabs

Measured 10,000 cycles,

low jitter input signal

20

50

ps

Jitter; 1-sigma

T

j1-s

Measured 10,000 cycles,

low jitter input signal

9

15

ps

SWITCHING WAVEFORMS

Duty Cycle Timing

t1

t2

VDD/2VDD/2 VDD/2

Output - Output Skew

VDD/2

T

SKEW

Output

PL102-10TI

PL102-10TI

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