ADG432BR

ADG431/ADG432/ADG433
REV. C
–4–
ABSOLUTE MAXIMUM RATINGS
(T
A
= 25°C unless otherwise noted.)
V
DD
to V
SS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 V
V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +25 V
V
SS
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –25 V
V
L
to GND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to V
DD
+ 0.3 V
Analog, Digital Inputs
2
. . . . . . . . . . V
SS
– 2 V to V
DD
+ 2 V or
30 mA, Whichever Occurs First
Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . 30 mA
Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
(Pulsed at 1 ms, 10% Duty Cycle max)
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Plastic Package, Power Dissipation . . . . . . . . . . . . . . 470 mW
θ
JA
, Thermal Impedance . . . . . . . . . . . . . . . . . . . . 117°C/W
Lead Temperature, Soldering (10 sec) . . . . . . . . . . . . 260°C
SOIC Package, Power Dissipation . . . . . . . . . . . . . . . 600 mW
θ
JA
, Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 77°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.
2
Overvoltages at IN, S or D will be clamped by internal diodes. Current should be
limited to the maximum ratings given.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADG431/ADG432/ADG433 features proprietary ESD protection circuitry, perma-
nent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
PIN CONFIGURATION
(DIP/SOIC)
TOP VIEW
(Not to Scale)
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
IN1
D1
S1
V
SS
GND
S4
D4
IN4
IN2
D2
S2
V
DD
V
L
S3
D3
IN3
ADG431
ADG432
ADG433
ORDERING GUIDE
Model Temperature Range Package Option
1
ADG431BN –40°C to +85°C N-16
ADG431BR –40°C to +85°C R-16A
ADG431ABR –40°C to +85°C R-16A
2
ADG432BN –40°C to +85°C N-16
ADG432BR –40°C to +85°C R-16A
ADG432ABR –40°C to +85°C R-16A
2
ADG433BN –40°C to +85°C N-16
ADG433BR –40°C to +85°C R-16A
ADG433ABR –40°C to +85°C R-16A
2
NOTES
1
N = Plastic DIP; R = 0.15" Small Outline IC (SOIC).
2
Trench isolated, latch-up proof parts. See Trench Isolation section.
TERMINOLOGY
V
DD
Most positive power supply potential.
V
SS
Most negative power supply potential in dual
supplies. In single supply applications, it may be
connected to GND.
V
L
Logic power supply (5 V).
GND Ground (0 V) reference.
S Source terminal. May be an input or output.
D Drain terminal. May be an input or output.
IN Logic control input.
R
ON
Ohmic resistance between D and S.
R
ON
vs. V
D
(V
S
) The variation in R
ON
due to a change in the ana-
log input voltage with a constant load current.
R
ON
Drift Change in R
ON
vs. temperature.
R
ON
Match Difference between the R
ON
of any two switches.
I
S
(OFF) Source leakage current with the switch “OFF.”
I
D
(OFF) Drain leakage current with the switch “OFF.”
I
D
, I
S
(ON) Channel leakage current with the switch “ON.”
V
D
(V
S
) Analog voltage on terminals D, S.
C
S
(OFF) “OFF” switch source capacitance.
C
D
(OFF) “OFF” switch drain capacitance.
C
D
, C
S
(ON) “ON” switch capacitance.
C
IN
Input Capacitance to ground of a digital input.
t
ON
Delay between applying the digital control input
and the output switching on.
t
OFF
Delay between applying the digital control input
and the output switching off.
t
D
“OFF” time or “ON” time measured between the
90% points of both switches, when switching
from one address state to another.
Crosstalk A measure of unwanted signal which is coupled
through from one channel to another as a result
of parasitic capacitance.
Off Isolation A measure of unwanted signal coupling through an
“OFF” switch.
Charge A measure of the glitch impulse transferred from the
Injection digital input to the analog output during switching.
WARNING!
ESD SENSITIVE DEVICE
V
D
OR V
S
– DRAIN OR SOURCE VOLTAGE – V
50
40
10
–20 –10
R
ON
01020
30
20
T
A
= 25C
V
L
= 5V
0
V
DD
= +15V
V
SS
= –15V
V
DD
= +10V
V
SS
= –10V
V
DD
= +12V
V
SS
= –12V
V
DD
= +5V
V
SS
= –5V
TPC 1. On Resistance as a Function of V
D
(V
S
) Dual
Supplies
V
D
OR V
S
DRAIN OR SOURCE VOLTAGE V
50
40
10
20 10
R
ON
01020
30
20
0
V
DD
= +15V
V
SS
= 15V
V
L
= +5V
125C
85C
25C
TPC 2. On Resistance as a Function of V
D
(V
S
) for Different
Temperatures
TEMPERATURE C
10
0.001
20 12040
LEAKAGE CURRENT nA
60 80 100
1
0.1
0.01
V
DD
= +15V
V
SS
= 15V
V
L
= +5V
140
V
S
= 15V
V
D
= 15V
I
S
(OFF)
I
D
(OFF)
I
D
(ON)
TPC 3. Leakage Currents as a Function of Temperature
V
D
OR V
S
DRAIN OR SOURCE VOLTAGE V
50
40
10
05
R
ON
10 15 20
30
20
T
A
= 25C
V
L
= 5V
0
V
DD
= 15V
V
SS
= 0V
V
DD
= 10V
V
SS
= 0V
V
DD
= 12V
V
SS
= 0V
V
DD
= 5V
V
SS
= 0V
TPC 4. On Resistance as a Function of V
D
(V
S
) Single
Supply
FREQUENCY Hz
100mA
100nA
10
10M100
I
SUPPLY
1k 10k 100k 1M
10mA
1mA
100A
10A
1A
V
DD
= +15V 4 SW
V
SS
= 15V
V
L
= +5V
1 SW
I+, I
I
L
TPC 5. Supply Current vs. Input Switching Frequency
V
D
OR V
S
DRAIN OR SOURCE VOLTAGE V
0.04
0.02
0.04
20 10
LEAKAGE CURRENT nA
01020
0.00
0.02
V
DD
= +15V
V
SS
= 15V
T
A
= +25C
V
L
= +5V
I
D
(ON)
I
S
(OFF)
I
D
(OFF)
TPC 6. Leakage Currents as a Function of V
D
(V
S
)
Typical Performance CharacteristicsADG431/ADG432/ADG433
REV. C
–5–
ADG431/ADG432/ADG433
REV. C
–6–
FREQUENCY Hz
120
100
40
100 10M1k
OFF ISOLATION dB
10k 100k 1M
80
60
V
DD
= +15V
V
SS
= 15V
V
L
= +5V
TPC 7. Off Isolation vs. Frequency
FREQUENCY Hz
110
100
60
100 10M1k
CROSSTALK dB
10k 100k 1M
90
80
70
V
DD
= +15V
V
SS
= 15V
V
L
= +5V
TPC 8. Crosstalk vs. Frequency
TRENCH ISOLATION
In the ADG431A, ADG432A and ADG433A, an insulating
oxide layer (trench) is placed between the NMOS and PMOS
transistors of each CMOS switch. Parasitic junctions, which
occur between the transistors in junction isolated switches, are
eliminated, the result being a completely latch-up proof switch.
In junction isolation, the N and P wells of the PMOS and NMOS
transistors from a diode that is reverse-biased under normal
operation. However, during overvoltage conditions, this diode
becomes forward biased. A silicon-controlled rectifier (SCR)
type circuit is formed by the two transistors causing a significant
amplification of the current which, in turn, leads to latch up.
With trench isolation, this diode is removed, the result being a
latch-up proof switch.
BURIED OXIDE LAYER
SUBSTRATE (BACKGATE)
T
R
E
N
C
H
T
R
E
N
C
H
T
R
E
N
C
H
P
+
P
+
P-CHANNEL
N
+
N
+
N-CHANNEL
P
N
V
G
V
D
V
S
V
G
V
D
V
S
Figure 1. Trench Isolation
APPLICATION
Figure 2 illustrates a precise, fast sample-and-hold circuit.
An AD845 is used as the input buffer while the output opera-
tional amplifier is an AD711. During the track mode, SW1 is
closed and the output V
OUT
follows the input signal V
IN
. In
the hold mode, SW1 is opened and the signal is held by the
hold capacitor C
H
.
Due to switch and capacitor leakage, the voltage on the hold
capacitor will decrease with time. The ADG431/ADG432/
ADG433 minimizes this droop due to its low leakage specifica-
tions. The droop rate is further minimized by the use of a
polystyrene hold capacitor. The droop rate for the circuit
shown is typically 30 µV/µs.
A second switch SW2, which operates in parallel with SW1, is
included in this circuit to reduce pedestal error. Since both
switches will be at the same potential, they will have a differen-
tial effect on the op amp AD711 which will minimize charge
injection effects. Pedestal error is also reduced by the compensa-
tion network R
C
and C
C
. This compensation network also reduces
the hold time glitch while optimizing the acquisition time. Using
the illustrated op amps and component values, the pedestal error
has a maximum value of 5 mV over the ± 10 V input range. Both
the acquisition and settling times are 850 ns.
+15V
15V
2200pF
R
C
75
C
C
1000pF
C
H
2200pF
V
OUT
ADG431
ADG432
ADG433
SW1
SW2
S
S
D
D
+15V +5V
15V
AD845
+15V
15V
V
IN
AD711
Figure 2. Fast, Accurate Sample-and-Hold

ADG432BR

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog Switch ICs LC2MOS Precision Quad SPST
Lifecycle:
New from this manufacturer.
Delivery:
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