RT8074
8
DS8074-07 November 2012www.richtek.com
©
Copyright 2012 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
Having a lower ripple current reduces not only the ESR
losses in the output capacitors but also the output voltage
ripple. Highest efficiency operation is achieved by reducing
ripple current at low frequency, but it requires a large
inductor to attain this goal.
For the ripple current selection, the value of ΔI
L
= 0.4 (I
MAX
)
will be a reasonable starting point. The largest ripple current
occurs at the highest V
IN
. To guarantee that the ripple
current stays below a specified maximum, the inductor
value should be chosen according to the following
equation :
OUT OUT
L(MAX) IN(MAX)
VV
L1
f x I V
⎡⎤⎡⎤
=−
⎢⎥⎢⎥
Δ
⎢⎥⎢⎥
⎣⎦⎣⎦
Using Ceramic Input and Output Capacitors
Higher value, lower cost ceramic capacitors are now
becoming available in smaller case sizes. Their high ripple
current, high voltage rating and low ESR make them ideal
for switching regulator applications. However, care must
be taken when these capacitors are used at the input and
output. When a ceramic capacitor is used at the input
and the power is supplied by a wall adapter through long
wires, a load step at the output can induce ringing at the
input V
IN
. At best, this ringing can couple to the output
and be mistaken as loop instability. At worst, a sudden
inrush of current through the long wires can potentially
cause a voltage spike at V
IN
large enough to damage the
part.
Slope Compensation and Inductor Peak Current
Slope compensation provides stability in constant
frequency architectures by preventing sub harmonic
oscillations at duty cycles greater than 50%. It is
accomplished internally by adding a compensating ramp
to the inductor current signal. Normally, the maximum
inductor peak current is reduced when slope compensation
is added. For the RT8074, however, a separate inductor
current signal is used to monitor over current condition,
so this keeps the maximum output current relatively
constant regardless of duty cycle.
Hiccup Mode Under Voltage Protection
A Hiccup Mode Under Voltage Protection (UVP) function
is provided for the IC. When the FB voltage drops below
half of the feedback reference voltage, V
REF
, the UVP
function will be triggered to auto soft-start the power stage
continuously until this event is cleared. The Hiccup Mode
UVP reduces input current in short circuit conditions and
prevents false triggering during soft-start process.
Under Voltage Lockout Threshold
The IC features input under voltage lockout protection
(UVLO). If the input voltage exceeds the UVLO rising
threshold voltage, the converter will reset and prepare the
PWM for operation. If the input voltage falls below the
UVLO falling threshold voltage during normal operation,
the device will stop switching. The UVLO rising and falling
threshold voltage has a hysteresis to prevent noise-caused
reset.
Thermal Considerations
For continuous operation, do not exceed absolute
maximum junction temperature. The maximum power
dissipation depends on the thermal resistance of the IC
package, PCB layout, rate of surrounding airflow, and
difference between junction and ambient temperature. The
maximum power dissipation can be calculated by the
following formula :
P
D(MAX)
= (T
J(MAX)
− T
A
) / θ
JA
where T
J(MAX)
is the maximum junction temperature, T
A
is
the ambient temperature, and θ
JA
is the junction to ambient
thermal resistance.
For recommended operating condition specifications, the
maximum junction temperature is 125°C. The junction to
ambient thermal resistance, θ
JA
, is layout dependent. For
SOP-8 (Exposed Pad) packages, the thermal resistance,
θ
JA
, is 75°C/W on a standard JEDEC 51-7 four-layer
thermal test board. The maximum power dissipation at T
A
= 25°C can be calculated by the following formula :
P
D(MAX)
= (125°C − 25°C) / (75°C/W) = 1.333W
for SOP-8 (Exposed Pad) package
The maximum power dissipation depends on the operating
ambient temperature for fixed T
J(MAX)
and thermal
resistance, θ
JA
. The derating curve in Figure 3 allows the
designer to see the effect of rising ambient temperature
on the maximum power dissipation.
