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HRF-AT4521-FL-TR

P1-P3P4-P6P7-P7
HRF-AT4521
31.0 dB, DC - 2.5GHz, 5 Bit Serial Digital Attenuator
The Honeywell HRF-AT4521 is a 5-bit digital attenuator that is ideal for use in
broadband communication system applications that require accuracy, speed and low
power consumption. The HRF-AT4521 is manufactured with Honeywell's patented
Silicon On Insulator (SOI) CMOS manufacturing technology, which provides the
performance of GaAs with the economy and integration capabilities of conventional
CMOS. These attenuators are DC coupled to improve lower operating frequency,
frequency response and reduce the number of DC bias points required.
FEATURES
Very Low DC Power Consumption
Attenuation In Steps From 1 dB To 31 dB
Single Positive Power Supply Voltage
Serial Data Interface
50 Ohm Impedance
DC-coupled, bi-directional RF path
Space Saving VQFN Surface Mount Packaging
Lead-free, RoHS compliant and halogen-free
RF ELECTRICAL SPECIFICATIONS @ + 25
o
C (1)
Results @ V
DD
= 5.0 +/- 10%, V
SS
= 0 unless otherwise stated, Z
0
= 50 Ohms
Contact Honeywell for relative performance at other supply configurations
Parameter
Test Condition
Frequency
Minimum
Typical
Maximum
Units
Insertion Loss
1.0 GHz
2.0 GHz
2.5 GHz
2.0
2.2
2.8
2.6
2.8
3.4
dB
dB
dB
1dB Compression
V
SS
= 0V, Input Power
V
SS
= - 3V, Input Power
2.0 GHz
2.0 GHz
22
28
dBm
dBm
Input IP3
V
SS
= 0V
Two-tone inputs, up to +5 dBm
@ 0 dBm attenuation
2.0 GHz
36
dBm
Input IP3
V
ss
= -3V
Two-tone inputs, up to + 5 dBm
@ 0 dBm attenuation
2.0 GHz
>36
dBm
Return Loss
Any Combination of Bits
-11
-13
dB
Attenuation Accuracy
All attenuation states
All attenuation states
All attenuation states
1.0 GHz
2.0 GHz
2.5 GHz
+ (0.25 + 2.5 %), - (0.10 + 5.0 %)
+ 0.45, - (0.20 + 8.0 %)
+ 0.35, - (-0.40 + 10.5%)
dB
dB
dB
Trise, Tfall
Ton, Toff (Tpd)
10% To 90%
50% Cntl To 90%/10%RF
10
15
nS
nS
T clock Period (Tprd)
T high / T low = ½ minimum clock period
50
nS
T data set up (Tsup)
Set up to rising edge of clock
5
nS
T data hold (Thld)
Data hold after rising edge of clock
2
nS
T latch set up (Tlsup)
Data set up to rising edge of OE
5
nS
Note 1 - For higher accuracy designs, please consider HRF-AT4610/HRF-AT4611.
HRF-AT4521
2 www.honeywell.com/microwave
FUNCTIONAL SCHEMATIC
DC ELECTRICAL SPECIFICATIONS @ + 25°C
Parameter
Minimum
Typical
Maximum
Units
V
DD
3.3
1
5.0
5.5
V
V
SS
-5.0
V
I
DD
<5.0
50
uA
CMOS Logic level (0)
0
0.8
V
CMOS Logic level (1)
V
DD
– 0.8
V
DD
V
Input Leakage Current
10
uA
Note 1, the performance curves are for V
DD
= +5.0 +/- 10%
ABSOLUTE MAXIMUM RATINGS
1
Parameter
Absolute Maximum
Units
Input Power
+ 35
dBm
V
DD
+6.0
V
V
SS
-5.5
V
ESD Voltage
2
400
V
Operating Temperature
-40 To +85
O
C
Storage Temperature
-65 To +125
O
C
Moisture Sensitivity Level
Level 3 @ 260
O
C
Digital Inputs
V
DD
+0.6 max to -0.6 min
V
Note
1 - Operation of this device beyond any of these parameters may cause permanent damage.
Note
2 - Although the HRF-AT4521 contains ESD protection circuitry on all digital inputs, precautions should be taken to
ensure that the Absolute Maximum Ratings are not exceeded.
Latch-Up: Unlike conventional CMOS digital attenuators, Honeywell's HRF-AT4521 is immune to latch-up.
RF In
RF Out
S4
S3
S0
S1
S2
16dB
8dB
4dB
2dB
1dB
ESD, Buffer, Level Shift
HRF- AT4521
www.honeywell.com/microwave 3
PIN CONFIGURATIONS
Pin
Function
Pin
Function
1
VDD
9
GROUND
2
GROUND
10
RF OUTPUT
3
RF INPUT
11
GROUND
4
GROUND
12
VSS
5
GROUND
13
GROUND
6
GROUND
14
OE
7
GROUND
15
CLK
8
GROUND
16
DATA
Note: Bottom ground plate must be grounded for proper RF performance.
SERIAL DATA LOAD
Serial data is shifted into the register on the rising edge of clock, MSB first. The state of “OE” will not affect the shifting of
data. The rising edge of the “OE” signal will be the clock for the transfer of shifted data. Latched new data occurs one
prop delay after the rising edge of “OE”. See the Electrical Spec Table for AC parameters.
TRUTH TABLE
S4
S3
S2
S1
S0
Output
0
0
0
0
0
1
1
0
0
0
0
1
0
1
0
0
0
1
0
0
1
0
0
1
0
0
0
1
0
1
0
0
0
0
1
Reference Input
1 dB
2 dB
4 dB
8 dB
16 dB
31 dB
Operation: Data on serial input D is clocked into internal registers on the low to high transition of the Clock signal (CK).
The register output is enabled when Output Enable (OE) is in the low state. "0" = CMOS Low, "1" = CMOS High.
P1-P3P4-P6P7-P7

HRF-AT4521-FL-TR

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Description:
RF ATTENUATOR 50OHM 16VQFN
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