Nexperia
74AUP1G3208
Low-power 3-input OR-AND gate
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Date of release: 7 March 2017
Document identifier: 74AUP1G3208
Contents
1 General description ............................................ 1
2 Features and benefits .........................................1
3 Ordering information .......................................... 2
4 Marking .................................................................2
5 Functional diagram ............................................. 2
6 Pinning information ............................................ 3
6.1 Pinning ...............................................................3
6.2 Pin description ................................................... 3
7 Functional description ........................................4
7.1 Logic configurations ...........................................4
8 Limiting values ....................................................5
9 Recommended operating conditions ................ 5
10 Static characteristics .......................................... 6
11 Dynamic characteristics .....................................9
11.1 Waveforms and test circuit .............................. 11
12 Package outline .................................................13
13 Abbreviations .................................................... 19
14 Revision history ................................................ 19
15 Legal information .............................................. 20
