DATA SHEET
2:4, LVDS Output Fanout Buffer, 2.5V IDT8SLVD1204I
IDT8SLVD1204I REVISION A 07/10/14 1 ©2014 Integrated Device Technology, Inc.
General Description
The IDT8SLVD1204I is a high-performance differential LVDS fanout
buffer. The device is designed for the fanout of high-frequency, very
low additive phase-noise clock and data signals. The
IDT8SLVD1204I is characterized to operate from a 2.5V power
supply. Guaranteed output-to-output and part-to-part skew
characteristics make the IDT8SLVD1204I ideal for those clock
distribution applications demanding well-defined performance and
repeatability. Two selectable differential inputs and four low skew
outputs are available. The integrated bias voltage reference enables
easy interfacing of single-ended signals to the device inputs. The
device is optimized for low power consumption and low additive
phase noise.
Features
• Four low skew, low additive jitter LVDS output pairs
• Two selectable differential clock input pairs
• Differential PCLK, nPCLK pairs can accept the following
differential input levels: LVDS, LVPECL
• Maximum input clock frequency: 2GHz
• LVCMOS/LVTTL interface levels for the control input select pin
• Output skew: 20ps (maximum)
• Propagation delay: 300ps (maximum)
• Low additive phase jitter, RMS; f
REF
= 156.25MHz, V
PP
= 1V,
10kHz - 20MHz: 95fs (maximum)
• Full 2.5V supply voltage
• Lead-free (RoHS 6), 16-Lead VFQFN packaging
• -40°C to 85°C ambient operating temperature
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
PCLK1
nPCLK1
VDD
Pullup/Pulldown
Pulldown
SEL
Pullup/Pulldown
0
1
PCLK0
nPCLK0
VDD
GND
Pullup/Pulldown
Pulldown
VDD
GND
Reference
Voltage
Generator
V
REF
GND
GND GND
1 2 3 4
12 11 10 9
13
14
15
16
8
7
6
5
Q2
nQ2
Q3
nQ3
VREF
nPCLK0
PCLK0
VDD
GND
SEL
PCLK1
nPCLK1
Q1
nQ0
Q0
nQ1
Pin Assignment
IDT8SLVD1204I
16 lead VFQFN
3.0mm x 3.0mm x 0.9mm package body
1.7mm x 1.7mm ePad
NL Package
Top View
Block Diagram