AD9410BSVZ Datasheet AD9410BSVZ | P7-P9

AD9410

Rev. A | Page 6 of 20

t

EH

t

EL

1/

f

S

t

A

t

SDS

t

CPD

SAMPLE N–2

SAMPLE N–1

SAMPLE N

SAMPLE N+1 SAMPLE N+2

SAMPLE N+3

SAMPLE N+4

SAMPLE N+5

SAMPLE N+6

t

V

t

PD

t

HDS

STATIC

STATIC INVALIDINVALID INVALID

INVALID

DATA N+1 DATA N+3

DATA N DATA N+2

DATA N+1

DATA N DATA N+2

INTERLEAVED DATA OUT

PARALLEL DATA OUT

A

IN

CLK+

DS

PORT A

D7 TO D0

PORT B

D7 TO D0

DCO

PORT A

D7 TO D0

PORT B

D7 TO D0

CLK–

DS

DCO

01679-002

Figure 2. Timing Diagram

AD9410

Rev. A | Page 7 of 20

ABSOLUTE MAXIMUM RATINGS

Table 5.

Parameter Rating

V

D

, V

CC

, V

DD

6 V

Analog Inputs 0 V to V

CC

+ 0.5 V

Digital Inputs 0 V to V

DD

+ 0.5 V

VREF

IN

0 V to V

D

+ 0.5 V

Digital Output Current 20 mA

Operating Temperature Range −55°C to +125°C

Storage Temperature Range −65°C to +150°C

Maximum Junction Temperature

1

150°C

1

Adequate dissipation of power from the AD9410 relies on all power and

ground pins of the device being soldered directly to a copper plane on a PCB.

In addition, the thermally enhanced package of the AD9410BSVZ has an

exposed paddle on the bottom that must be soldered to a large copper

plane, which, for convenience, can be the ground plane. Sockets for package

style of the AD9410 device are not recommended.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

EXPLAINATION OF TEST LEVELS

Test Level

I. 100% production tested.

II. 100% production tested at 25°C and sample tested at

specified temperatures.

III. Sample tested only.

IV. Parameter is guaranteed by design and characterization

testing.

V. Parameter is a typical value only.

VI. 100% production tested at 25°C; guaranteed by

design and characterization testing for industrial

temperature range.

ESD CAUTION

AD9410

Rev. A | Page 8 of 20

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

01679-003

PIN 1

IDENTIFIER

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23 24

25 26

27

28 29 30 31

32

33

34 35

36 37 38 39 40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

6162636465666768697071727374757677787980

AD9410

TOP VIEW

80-LEAD THIN QUAD FLAT PACKAGE

(Not to Scale)

AGND

V

CC

REF

OUT

REF

IN

DNC

V

CC

AGND

A

IN

AGND

V

CC

V

CC

AGND

CLK+

AGND

V

DD

DGND

D

A4

D

A3

D

A2

D

A1

D

A0

(LSB)

V

DD

DGND

DCO

DGND

V

DD

OR

B

D

B9

(MSB)

D

B8

D

B7

D

B6

D

B5

V

DD

I/P

DFS

AGND

V

D

V

D

AGND

V

D

V

D

DGND

V

DD

OR

A

D

A9

(MSB)

D

A8

D

A7

D

A6

D

A5

AGND

DS

AGND

V

D

V

D

AGND

V

D

V

D

DGND

V

DD

(LSB) D

B0

D

B1

D

B2

D

B3

D

B4

DGND

A

IN

CLK–

DS

DNC = DO NOT CONNECT.

Figure 3. Pin Configuration

Table 6. Pin Function Descriptions

Pin No. Mnemonic Function

1, 2, 8, 9, 12, 13, 16,

17, 20, 21, 24, 27, 28,

29, 30, 71, 72, 73, 74,

77, 78

AGND Analog Ground.

3, 7, 14, 15 V

CC

5 V Supply. (Regulate to within ±5%.)

4 REF

OUT

Internal Reference Output.

5 REF

IN

Internal Reference Input.

6 DNC Do Not Connect.

10 A

IN

Analog Input—True.

11

A

IN

Analog Input—Complement.

18 CLK+ Clock Input—True.

19 CLK− Clock Input—Complement.

22 DS Data Sync (Input)—True. Tie low if not used.

23

DS

Data Sync (Input)—Complement. Float and decouple with 0.1 μF capacitor if not used.

25, 26, 31, 32, 69, 70,

75, 76

V

D

3.3 V Analog Supply. (Regulate to within ±5%.)

33, 40, 49, 52, 59, 68 DGND Digital Ground.

34, 41, 48, 53, 60, 67 V

DD

3.3 V Digital Output Supply. (2.5 V to 3.6 V)

35 to 39 D

B0

to D

B4

Digital Data Output for Channel B. (LSB = D

B0

.)

42 to 46 D

B5

to D

B9

Digital Data Output for Channel B. (MSB = D

B9

.)

47 OR

B

Data Overrange for Channel B.

50

DCO

Clock Output—Complement.

AD9410BSVZ

AD9410BSVZ

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