ISL6719ARZ-T

ISL6719
7
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COMPA, COMPB
A compensating capacitor is placed between COMPA and
COMPB to stabilize the control loop. The values may vary
depending on the output load and capacitance applied between
VSW and GND, but for all applications having a 1.0µF load
capacitor, a 220pF compensation capacitor is recommended.
The voltage at COMPA is nominally 0.7V. The voltage at COMPB
is nominally VSW +5.0V.
Functional Description
Features
The control circuitry used in Telecom/Datacom DC/DC
converters typically requires an operating bias voltage
significantly lower than the source voltage available to the
converter. Many applications use a discrete linear regulator from
the input source to create the bias supply. Often an auxiliary
winding from the power transformer is used to supplement or
replace the linear supply once the converter is operating. The
auxiliary winding bias voltage may require regulation as well to
minimize the voltage variation inherent in slave windings. When
implemented discretely, this circuitry occupies significant PWB
area, a considerable problem in today’s high density converters.
The ISL6719 linear regulator simplifies the start-up and
operating bias circuitry needed in Telecom and Datacom DC/DC
converters by integrating these functions, and more, in a small
3mm x 3mm DFN package.
AUXIN
AUXIN is the auxiliary input of the ISL6719, accepting bias
voltage whenever the input source voltage, VPWR, is above its
undervoltage lockout (UVLO) threshold. The VSW selects AUXIN
as its source when it is capable supporting the load on VSW.
Otherwise VPWR is selected.
AUXIN can accept voltages up to 40V maximum. Voltages in
excess of 40V, including transients, will cause permanent
damage to the device. Care should be taken when connecting
external sources through very long traces or lead wires. The
lead inductance may cause unexpected transients in excess of
the device’s ratings. In such circumstances it is recommended
that a small resistor be placed between AUXIN and the
external source to dampen the transient. A value of 10 to
100 is usually sufficient.
VSW
The VSW is the switched output and may be turned on and off
using the ENABLE or ENABLE_N pins. The VSW is adjustable
from 1.5V to 20V, but must always be at least 6.2V lower than
VPWR at rated load. Additionally, VSW must be at least 3.0V
lower than AUXIN for it to function as the source for VSW. As the
differential voltage between AUXIN and VSW drops below 3.0V,
the input current will shift from AUXIN to VPWR. The voltage
headroom required is load dependent (see Figures 1 and 2). The
VSW preferentially uses AUXIN as its input source, but if AUXIN
is unable to supply adequate voltage, VPWR is selected as the
alternate input source. The VSW is capable of delivering up to
100mA continuously, depending on power dissipation and the
thermal environment in which the device is placed.
The output voltage is adjusted using the VSW_FB input. The
VSW is set with a resistor divider from VSW to ground with the
central node connected to VSW_FB. Refer to Figure 5.
Referring to Equation 1, the V
REF
is nominally 1.5V and I
BIAS
has a maximum value of 1.5µA. The error introduced by the
VSW_FB bias current can be minimized by making the product
of R
1
x I
BIAS
small, relative to the magnitude of the desired
output voltage. For example, setting R
1
x I
BIAS
equal to 0.5%
of VSW yields a value for R
1
equal to 3.33 x VSW (k).
The VSW requires an external compensation capacitor to
remain stable across the output adjustment range, output
capacitance and loading. A value of 220pF between COMPA
and COMPB is recommended for all operating conditions with
a nominal load capacitance of 1.0µF (0.47µF to 1.5µF). The
VSW requires a minimum load of 3mA.
VSW V
REF
R
1
R
2
+
R
2
---------------------
I
BIAS
R
1
= V
(EQ. 1)
FIGURE 5. VSW ADJUSTMENT AND COMPENSATION
ISL6719
8
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July 15, 2014
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Figure 6 depicts the transient response of VSW during a 10mA
to 100mA step load when AUXIN is set to 15V and VPWR is set
to 18V.
VPWR
VPWR provides the source voltage for the IC and load until
AUXIN is back biased. VSW is disabled and the IC operates in a
standby (low power consumption) mode when UVLO is active.
If the application requires high currents or longer start-up
times than the thermal protection allows, the device
dissipation may be reduced by adding a resistor or resistors in
series between the input voltage and VPWR. The dropping
resistance must be selected such that VPWR remains above
the UVLO threshold of VPWR and at least 6.2V greater than
VSW under maximum load and minimum input voltage to
maintain regulation.
ENABLE, ENABLE_N
The ENABLE and ENABLE_N are complementary inputs used to
turn VSW on and off. Both polarities of the enable function are
provided to ease the interface to the application. The VSW may
be enabled by either ENABLE or ENABLE_N, but both inputs
must be logically false to disable the output. Each enable input
has a nominal 100k pull-up resistor to 5V.
The inputs can accept voltages up to 6V maximum down to
0.3V below signal ground. Voltages beyond these limits,
including transients, may cause permanent damage to the
device. Care should be taken when connecting signal sources
through long connections or if significant ground shift could
occur between the source and the input. In such
circumstances, it is recommended that appropriate clamping
networks be used to prevent possible electrical overstress.
Over-Temperature Protection
The ISL6719 has an over-temperature shutdown mechanism
to protect the device from excessive dissipation. The VSW
shutdown occurs approximately at +150°C. The hysteresis is
large so that the IC has sufficient time to operate at start-up
loading levels without re-triggering the over-temperature
protection.
FIGURE 6. VSW TRANSIENT RESPONSE, 10mA TO 100mA STEP,
VPWR = 18V, AUXIN = 15V, VSW = 12V
TRACE 1: VSW
TRACE 2: I
VSW
FIGURE 7. ADDING DROPPING RESISTORS TO VPWR
V
IN
1
COMPB
2
5
7
8
9
3
4
6
COMPA
ENABLE
ENABLE
_N
GND
VPWR
AUXIN
VSW
VSW_FB
TABLE 1. ENABLE, ENABLE_N TRUTH TABLE
INPUTS OUTPUT
ENABLE ENABLE_N VSW
00ON
01OFF
10ON
11ON
ISL6719
9
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in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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FN6555.2
July 15, 2014
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Dual Flat No-Lead Plastic Package (DFN)
//
NX (b)
SECTION "C-C"
FOR ODD TERMINAL/SIDE
e
CC
4
C
L
TERMINAL TIP
(A1)
BOTTOM VIEW
A
5
AREA
INDEX
C
C
0.10
0.08
SIDE VIEW
0.15
2X
E
A
B
C0.15
D
TOP
VIEW
CB
2X
5
7
AREA
INDEX
NX L
E2
E2/2
REF.
e
N
(Nd-1)Xe
(DATUM A)
(DATUM B)
4
0.10
76
D2
BAC
N-1
12
PLANE
SEATING
C
A
A3
NX b
D2/2
NX k
8
L
M
L9.3x3
9 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE
SYMBOL
MILLIMETERS
NOTESMIN NOMINAL MAX
A
0.80 0.90 1.00
-
A1 - -
0.05
-
A3 0.20 REF -
b
0.20 0.25 0.30
4, 7
D 3.00 BSC -
D2
1.85 2.00 2.10
6, 7
E 3.00 BSC -
E2
0.80 0.95 1.05
6, 7
e 0.50 BSC -
k
0.60
---
L
0.25 0.35 0.45
7
N92
Rev. 0 3/06
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. All dimensions are in millimeters. Angles are in degrees.
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
6. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
7. Nominal dimensions are provided to assist with PCB Land Pattern
Design efforts, see Intersil Technical Brief TB389.
8. COMPLIANT TO JEDEC MO-229-WEED-3 except for dimensions E2 &
D2.

ISL6719ARZ-T

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Linear Voltage Regulators 100V LINEAR BIAS SUPPLY 3X3
Lifecycle:
New from this manufacturer.
Delivery:
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