The Smart Timing Choice
The Smart Timing Choice
SiTime Corporation 990 Almanor Avenue, Sunnyvale, CA 94085 (408) 328-4400 www.sitime.com
Rev. 1.5 Revised November 12, 2015
SiT5022
220-625 MHz High Performance Differential (VC) TCXO
Features Applications
Any frequency between 220 MHz and 625 MHz accurate to 6 decimal
places
SATA, SAS, 10GB Ethernet, Fibre Channel, PCI-Express
Networking, broadband, instrumentation
LVPECL and LVDS output signaling types
0.6ps RMS phase jitter (random) over 12 kHz to 20 MHz bandwidth
Frequency stability as low as ±5 ppm. Contact SiTime for tighter
stability options
Industrial and extended commercial temperature ranges
Industry-standard packages: 3.2 x 2.5, 5.0 x 3.2 and 7.0 x 5.0 mm
For frequencies lower than 220 MHz, refer to SiT5021 datasheet
Electrical Characteristics
Parameter and Conditions Symbol Min. Typ. Max. Unit Condition
LVPECL and LVDS, Common Electrical Characteristics
Supply Voltage Vdd 2.97 3.3 3.63 V
2.25 2.5 2.75 V
2.25 – 3.63 V Termination schemes in Figures 1 and 2 - XX ordering code
Output Frequency Range f 220 – 625 MHz
Initial Tolerance F_init -2 – 2 ppm At 25°C after two reflows
Stability Over Temperature F_stab -5 – +5 ppm
Over operating temperature range at rated nominal power
supply voltage and load.
Contact SiTime for tighter stability options.
Supply Voltage F_vdd – 50 – ppb ±10% Vdd
Output Load F_load – 0.1 – ppm 15 pF ±10% of load
First Year Aging F_aging1 -2.5 – +2.5 ppm 25°C
10-year Aging F_aging10 -5 – +5 ppm 25°C
Operating Temperature Range T_use
-40 – +85 °C Industrial
-20 – +70 °C Extended Commercial
Pull Range PR ±12.5, ±25, ±50 ppm
Upper Control Voltage VC_U Vdd-0.1 – – V All Vdds. Voltage at which maximum deviation is guaranteed.
Control Voltage Range VC_L – – 0.1 V
Control Voltage Input Impedance Z_vc 100 – – k
Frequency Change Polarity – Positive slope –
Control Voltage -3dB Bandwidth V_BW – – 8 kHz
Input Voltage High VIH 70% – – Vdd
Pin 1, OE or ST
Input Voltage Low VIL – – 30% Vdd
Pin 1, OE or ST
Input Pull-up Impedance Z_in
– 100 250 kΩ
Pin 1, OE logic high or logic low, or ST
logic high
2––MΩ
Pin 1, ST
logic low
Start-up Time T_start – 6 10 ms Measured from the time Vdd reaches its rated minimum value.
Resume Time T_resume – 6 10 ms
In Standby mode, measured from the time ST
pin crosses
Duty Cycle DC 45 – 55 % Contact SiTime for tighter duty cycle
LVPECL, DC and AC Characteristics
Current Consumption Idd – 61 69 mA Excluding Load Termination Current, Vdd = 3.3V or 2.5V
OE Disable Supply Current I_OE – – 35 mA OE = Low
Output Disable Leakage Current I_leak – – 1 AOE = Low
Standby Current I_std – – 100 A
ST
= Low, for all Vdds
Maximum Output Current I_driver – – 30 mA Maximum average current drawn from OUT+ or OUT-
Output High Voltage VOH Vdd-1.1 – Vdd-0.7 V See Figure 1(a)
Output Low Voltage VOL Vdd-1.9 – Vdd-1.5 V See Figure 1(a)
Output Differential Voltage Swing V_Swing 1.2 1.6 2.0 V See Figure 1(b)
Rise/Fall Time Tr, Tf – 300 500 ps 20% to 80%, see Figure 1(a)
OE Enable/Disable Time T_oe – – 115 ns
f = 220 MHz - For other frequencies, T_oe = 100ns + 3 period
RMS Period Jitter T_jitt – 1.2 1.7 ps f = 266 MHz, VDD = 3.3V or 2.5V
– 1.2 1.7 ps f = 312.5 MHz, VDD = 3.3V or 2.5V
– 1.2 1.7 ps f = 622.08 MHz, VDD = 3.3V or 2.5V
RMS Phase Jitter (random) T_phj – 0.6 0.85 ps f = 312.5 MHz, Integration bandwidth = 12 kHz to 20 MHz, all
Vdds
